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t23x-public-dts/overlay/tegra234-p3767-0000-common-hdr40.dtsi
Gautham Srinivasan 07b71d4603 t23x: overlay: display pin state for i2c and uart 
In Jetson-IO, I2C and UART pins are configured by default,
and there is no option to disable or display them as enabled.
By adding the appropriate "nvidia,function" value, Jetson-IO
updates the "Configure header pins manually" section to show
the pin state, allowing the user to enable or disable these pins.

Also, add the input and tristate values so that the pin can be
enabled back to the right configuration.

Bug 3866629

Change-Id: I2c01ac7355259e4a3e0a10905699b5dfbbbaf177
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3219025
(cherry picked from commit 332e56ee15)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3221548
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
2024-10-06 10:53:15 -07:00

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// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2021-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/*
* Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
/ {
overlay-name = "Jetson 40pin Header";
fragment@0 {
target = <&pinmux>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&jetson_io_pinmux>;
jetson_io_pinmux: exp-header-pinmux {
hdr40-pin7 {
nvidia,pins = "soc_gpio59_pac6";
nvidia,function = "aud";
nvidia,pin-label = "aud_mclk";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
hdr40-pin8 {
nvidia,pins = "uart1_tx_pr2";
nvidia,function = "uarta";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
hdr40-pin10 {
nvidia,pins = "uart1_rx_pr3";
nvidia,function = "uarta";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin11 {
nvidia,pins = "uart1_rts_pr4";
nvidia,function = "uarta";
nvidia,pin-group = "uarta-cts/rts";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
hdr40-pin12 {
nvidia,pins = "soc_gpio41_ph7";
nvidia,function = "i2s2";
nvidia,pin-label = "i2s2_sclk";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin13 {
nvidia,pins = "spi3_sck_py0";
nvidia,function = "spi3";
nvidia,pin-label = "spi3_sck";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin15 {
nvidia,pins = "soc_gpio39_pn1";
nvidia,function = "gp";
nvidia,pin-group = "pwm1";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
hdr40-pin16 {
nvidia,pins = "spi3_cs1_py4";
nvidia,function = "spi3";
nvidia,pin-label = "spi3_cs1";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin18 {
nvidia,pins = "spi3_cs0_py3";
nvidia,function = "spi3";
nvidia,pin-label = "spi3_cs0";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin19 {
nvidia,pins = "spi1_mosi_pz5";
nvidia,function = "spi1";
nvidia,pin-label = "spi1_dout";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin21 {
nvidia,pins = "spi1_miso_pz4";
nvidia,function = "spi1";
nvidia,pin-label = "spi1_din";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin22 {
nvidia,pins = "spi3_miso_py1";
nvidia,function = "spi3";
nvidia,pin-label = "spi3_din";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin23 {
nvidia,pins = "spi1_sck_pz3";
nvidia,function = "spi1";
nvidia,pin-label = "spi1_sck";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin24 {
nvidia,pins = "spi1_cs0_pz6";
nvidia,function = "spi1";
nvidia,pin-label = "spi1_cs0";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin26 {
nvidia,pins = "spi1_cs1_pz7";
nvidia,function = "spi1";
nvidia,pin-label = "spi1_cs1";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin29 {
nvidia,pins = "soc_gpio32_pq5";
nvidia,function = "extperiph3";
nvidia,pin-group = "extperiph3_clk";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
hdr40-pin31 {
nvidia,pins = "soc_gpio33_pq6";
nvidia,function = "extperiph4";
nvidia,pin-group = "extperiph4_clk";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
hdr40-pin32 {
nvidia,pins = "soc_gpio19_pg6";
nvidia,function = "gp";
nvidia,pin-group = "pwm7";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
hdr40-pin33 {
nvidia,pins = "soc_gpio21_ph0";
nvidia,function = "gp";
nvidia,pin-group = "pwm5";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
hdr40-pin35 {
nvidia,pins = "soc_gpio44_pi2";
nvidia,function = "i2s2";
nvidia,pin-label = "i2s2_fs";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin36 {
nvidia,pins = "uart1_cts_pr5";
nvidia,function = "uarta";
nvidia,pin-group = "uarta-cts/rts";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin37 {
nvidia,pins = "spi3_mosi_py2";
nvidia,function = "spi3";
nvidia,pin-label = "spi3_dout";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin38 {
nvidia,pins = "soc_gpio43_pi1";
nvidia,function = "i2s2";
nvidia,pin-label = "i2s2_din";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin40 {
nvidia,pins = "soc_gpio42_pi0";
nvidia,function = "i2s2";
nvidia,pin-label = "i2s2_dout";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
};
};
fragment@1 {
target = <&pinmux_aon>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&jetson_io_pinmux_aon>;
jetson_io_pinmux_aon: exp-header-pinmux {
hdr40-pin3 {
nvidia,pins = "gen8_i2c_sda_pdd2";
nvidia,pin-label = "i2c8";
nvidia,function = "i2c8";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin5 {
nvidia,pins = "gen8_i2c_scl_pdd1";
nvidia,pin-label = "i2c8";
nvidia,function = "i2c8";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin27 {
nvidia,pins = "gen2_i2c_sda_pdd0";
nvidia,function = "i2c2";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
hdr40-pin28 {
nvidia,pins = "gen2_i2c_scl_pcc7";
nvidia,function = "i2c2";
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
};
};
};
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