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16fbe94504
The recent version of the FSI FW has updated it to include multi-core
FSI support where CCPLEX can communicate with multiple FSI cores, using
per core memory carveouts. This CL reflects the changes that it is
needed to accomplish that, specifically it adds mapping of the mailbox
to each core. While at it, it also corrects the epl DT node in line with
latest changes done in the safety SOC dtsi file otherwise it will create
two epl nodes which is not desirable.
JIRA L4T-4468
Change-Id: I782b57f67c553739ac76ab835da731ceb9a63c67
Signed-off-by: Dipen Patel <dipenp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2997185
(cherry picked from commit 3382ef1179 in rel-36)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3046292
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>