mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 17:30:17 +03:00
a7a7af00d8
Add DT binding headers, non-upstreamed version, which
are used for SOC and platform DTS/DTSI. These headers
are in staging state and taken from the
hardware/nvidia/soc/generic-dts/tegra/include/nvidia-oot.
Bug 4078385
Change-Id: Ia482b55e44c708ce5cab7d1fbcb8abfc07f4e440
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
164 lines
5.6 KiB
C
164 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_INTERRUPT_TEGRAT234_IRQ_H
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#define _DT_BINDINGS_INTERRUPT_TEGRAT234_IRQ_H
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#define TEGRA234_IRQ_I2C1 25
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#define TEGRA234_IRQ_I2C2 26
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#define TEGRA234_IRQ_I2C3 27
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#define TEGRA234_IRQ_I2C4 28
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#define TEGRA234_IRQ_I2C5 29
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#define TEGRA234_IRQ_I2C6 30
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#define TEGRA234_IRQ_I2C7 31
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#define TEGRA234_IRQ_I2C8 32
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#define TEGRA234_IRQ_I2C9 33
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#define TEGRA234_IRQ_UFSHC 44
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#define TEGRA234_IRQ_SDMMC1 62
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#define TEGRA234_IRQ_SDMMC3 64
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#define TEGRA234_IRQ_SDMMC4 65
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#define TEGRA234_IRQ_UARTA 112
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#define TEGRA234_IRQ_UARTB 113
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#define TEGRA234_IRQ_UARTC 114
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#define TEGRA234_IRQ_UARTD 115
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#define TEGRA234_IRQ_UARTE 116
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#define TEGRA234_IRQ_UARTF 117
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#define TEGRA234_IRQ_UARTG 118
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#define TEGRA234_IRQ_UARTH 207
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#define TEGRA234_IRQ_UARTI 285
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#define TEGRA234_IRQ_UARTJ 286
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#define TEGRA234_IRQ_EQOS_TX0 186
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#define TEGRA234_IRQ_EQOS_TX1 187
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#define TEGRA234_IRQ_EQOS_TX2 188
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#define TEGRA234_IRQ_EQOS_TX3 189
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#define TEGRA234_IRQ_EQOS_RX0 190
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#define TEGRA234_IRQ_EQOS_RX1 191
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#define TEGRA234_IRQ_TACH0 192
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#define TEGRA234_IRQ_TACH1 193
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#define TEGRA234_IRQ_EQOS_COMMON 194
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#define TEGRA234_IRQ_EQOS_POWER 195
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#define TEGRA234_IRQ_SATA 197
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#define TEGRA234_IRQ_ACTMON 210
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#define TEGRA234_IRQ_GPIO0_0 288
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#define TEGRA234_IRQ_GPIO0_1 289
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#define TEGRA234_IRQ_GPIO0_2 290
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#define TEGRA234_IRQ_GPIO0_3 291
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#define TEGRA234_IRQ_GPIO0_4 292
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#define TEGRA234_IRQ_GPIO0_5 293
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#define TEGRA234_IRQ_GPIO0_6 294
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#define TEGRA234_IRQ_GPIO0_7 295
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#define TEGRA234_IRQ_GPIO1_0 296
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#define TEGRA234_IRQ_GPIO1_1 297
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#define TEGRA234_IRQ_GPIO1_2 298
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#define TEGRA234_IRQ_GPIO1_3 299
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#define TEGRA234_IRQ_GPIO1_4 300
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#define TEGRA234_IRQ_GPIO1_5 301
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#define TEGRA234_IRQ_GPIO1_6 302
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#define TEGRA234_IRQ_GPIO1_7 303
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#define TEGRA234_IRQ_GPIO2_0 304
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#define TEGRA234_IRQ_GPIO2_1 305
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#define TEGRA234_IRQ_GPIO2_2 306
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#define TEGRA234_IRQ_GPIO2_3 307
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#define TEGRA234_IRQ_GPIO2_4 308
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#define TEGRA234_IRQ_GPIO2_5 309
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#define TEGRA234_IRQ_GPIO2_6 310
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#define TEGRA234_IRQ_GPIO2_7 311
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#define TEGRA234_IRQ_GPIO3_0 312
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#define TEGRA234_IRQ_GPIO3_1 313
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#define TEGRA234_IRQ_GPIO3_2 314
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#define TEGRA234_IRQ_GPIO3_3 315
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#define TEGRA234_IRQ_GPIO3_4 316
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#define TEGRA234_IRQ_GPIO3_5 317
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#define TEGRA234_IRQ_GPIO3_6 318
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#define TEGRA234_IRQ_GPIO3_7 319
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#define TEGRA234_IRQ_GPIO4_0 320
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#define TEGRA234_IRQ_GPIO4_1 321
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#define TEGRA234_IRQ_GPIO4_2 322
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#define TEGRA234_IRQ_GPIO4_3 323
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#define TEGRA234_IRQ_GPIO4_4 324
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#define TEGRA234_IRQ_GPIO4_5 325
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#define TEGRA234_IRQ_GPIO4_6 326
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#define TEGRA234_IRQ_GPIO4_7 327
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#define TEGRA234_IRQ_GPIO5_0 328
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#define TEGRA234_IRQ_GPIO5_1 329
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#define TEGRA234_IRQ_GPIO5_2 330
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#define TEGRA234_IRQ_GPIO5_3 331
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#define TEGRA234_IRQ_GPIO5_4 332
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#define TEGRA234_IRQ_GPIO5_5 333
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#define TEGRA234_IRQ_GPIO5_6 334
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#define TEGRA234_IRQ_GPIO5_7 335
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#define TEGRA234_IRQ_AON_GPIO_0 56
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#define TEGRA234_IRQ_AON_GPIO_1 57
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#define TEGRA234_IRQ_AON_GPIO_2 58
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#define TEGRA234_IRQ_AON_GPIO_3 59
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#define TEGRA234_IRQ_BPMP_WDT_REMOTE 14
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#define TEGRA234_IRQ_SPE_WDT_REMOTE 15
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#define TEGRA234_IRQ_SCE_WDT_REMOTE 16
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#define TEGRA234_IRQ_TOP_WDT_REMOTE 17
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#define TEGRA234_IRQ_AOWDT_REMOTE 18
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#define TEGRA234_IRQ_RCE_WDT_REMOTE 19
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#define TEGRA234_IRQ_APE_WDT_REMOTE 20
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#define TEGRA234_IRQ_TOP0_HSP_SHARED_0 120
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#define TEGRA234_IRQ_TOP0_HSP_SHARED_1 121
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#define TEGRA234_IRQ_TOP0_HSP_SHARED_2 122
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#define TEGRA234_IRQ_TOP0_HSP_SHARED_3 123
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#define TEGRA234_IRQ_TOP0_HSP_SHARED_4 124
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#define TEGRA234_IRQ_TOP0_HSP_SHARED_5 125
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#define TEGRA234_IRQ_TOP0_HSP_SHARED_6 126
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#define TEGRA234_IRQ_TOP0_HSP_SHARED_7 127
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#define TEGRA234_IRQ_TOP1_HSP_SHARED_0 128
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#define TEGRA234_IRQ_TOP1_HSP_SHARED_1 129
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#define TEGRA234_IRQ_TOP1_HSP_SHARED_2 130
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#define TEGRA234_IRQ_TOP1_HSP_SHARED_3 131
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#define TEGRA234_IRQ_TOP1_HSP_SHARED_4 132
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#define TEGRA234_IRQ_AON_HSP_SHARED_1 133
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#define TEGRA234_IRQ_AON_HSP_SHARED_2 134
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#define TEGRA234_IRQ_AON_HSP_SHARED_3 135
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#define TEGRA234_IRQ_AON_HSP_SHARED_4 136
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#define TEGRA234_IRQ_BPMP_HSP_SHARED_1 137
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#define TEGRA234_IRQ_BPMP_HSP_SHARED_2 138
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#define TEGRA234_IRQ_BPMP_HSP_SHARED_3 139
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#define TEGRA234_IRQ_BPMP_HSP_SHARED_4 140
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#define TEGRA234_IRQ_SCE_HSP_SHARED_1 141
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#define TEGRA234_IRQ_SCE_HSP_SHARED_2 142
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#define TEGRA234_IRQ_SCE_HSP_SHARED_3 143
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#define TEGRA234_IRQ_SCE_HSP_SHARED_4 144
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#define TEGRA234_IRQ_RCE_HSP_SHARED_1 182
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#define TEGRA234_IRQ_RCE_HSP_SHARED_2 183
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#define TEGRA234_IRQ_RCE_HSP_SHARED_3 184
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#define TEGRA234_IRQ_RCE_HSP_SHARED_4 185
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#define TEGRA234_IRQ_PMIC_EXT_INTR 209
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#define TEGRA234_IRQ_HSIO_L0_P2U 336
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#define TEGRA234_IRQ_HSIO_L1_P2U 337
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#define TEGRA234_IRQ_HSIO_L2_P2U 338
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#define TEGRA234_IRQ_HSIO_L3_P2U 339
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#define TEGRA234_IRQ_HSIO_L4_P2U 340
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#define TEGRA234_IRQ_HSIO_L5_P2U 341
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#define TEGRA234_IRQ_HSIO_L6_P2U 342
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#define TEGRA234_IRQ_HSIO_L7_P2U 343
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#define TEGRA234_IRQ_NVHS_L0_P2U 344
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#define TEGRA234_IRQ_NVHS_L1_P2U 345
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#define TEGRA234_IRQ_NVHS_L2_P2U 346
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#define TEGRA234_IRQ_NVHS_L3_P2U 347
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#define TEGRA234_IRQ_NVHS_L4_P2U 348
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#define TEGRA234_IRQ_NVHS_L5_P2U 349
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#define TEGRA234_IRQ_NVHS_L6_P2U 350
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#define TEGRA234_IRQ_NVHS_L7_P2U 351
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#define TEGRA234_IRQ_GBE_L0_P2U 203
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#define TEGRA234_IRQ_GBE_L1_P2U 220
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#define TEGRA234_IRQ_GBE_L2_P2U 221
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#define TEGRA234_IRQ_GBE_L3_P2U 222
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#define TEGRA234_IRQ_GBE_L4_P2U 108
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#define TEGRA234_IRQ_GBE_L5_P2U 109
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#define TEGRA234_IRQ_GBE_L6_P2U 110
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#define TEGRA234_IRQ_GBE_L7_P2U 111
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#endif
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