mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
8f0cbdad83
These preprocessor conditionals were a temporary step to facilitate step by step reviews. Remove them and fix indentation. Bug 4290389 Change-Id: Iecdbdf1869bec00538530d59420622d8563a116a Signed-off-by: Brad Griffis <bgriffis@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3000004 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Gautham Srinivasan <gauthams@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
196 lines
5.7 KiB
Devicetree
196 lines
5.7 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include <dt-bindings/power/tegra234-powergate.h>
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/ {
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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fb0_reserved: framebuffer@0,0 {
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compatible = "framebuffer";
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reg = <0x00 0x00 0x00 0x00>;
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iommu-addresses = <&display 0x0 0x0 0x0 0x0>;
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no-map;
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status = "disabled";
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};
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};
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dce@d800000 {
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compatible = "nvidia,tegra234-dce";
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reg = <0x0 0x0d800000 0x0 0x00800000>;
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interrupts =
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<0 376 0x4>,
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<0 377 0x4>;
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interrupt-names = "wdt-remote",
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"dce-sm0";
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iommus = <&smmu_niso0 TEGRA234_SID_DCE>;
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status = "disabled";
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};
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display: display@13800000 {
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compatible = "nvidia,tegra234-display";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
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nvidia,num-dpaux-instance = <1>;
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reg-names = "nvdisplay", "dpaux0", "hdacodec", "mipical";
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reg = <0x0 0x13800000 0x0 0xEFFFF /* nvdisplay */
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0x0 0x155C0000 0x0 0xFFFF /* dpaux0 */
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0x0 0x0242c000 0x0 0x1000 /* hdacodec */
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0x0 0x03990000 0x0 0x10000>; /* mipical */
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interrupt-names = "nvdisplay", "dpaux0", "hdacodec";
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interrupts = <0 416 4
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0 419 4
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0 61 4>;
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nvidia,bpmp = <&bpmp>;
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clocks = <&bpmp TEGRA234_CLK_HUB>,
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<&bpmp TEGRA234_CLK_DISP>,
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<&bpmp TEGRA234_CLK_NVDISPLAY_P0>,
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<&bpmp TEGRA234_CLK_NVDISPLAY_P1>,
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<&bpmp TEGRA234_CLK_DPAUX>,
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<&bpmp TEGRA234_CLK_FUSE>,
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<&bpmp TEGRA234_CLK_DSIPLL_VCO>,
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<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTPN>,
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<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTA>,
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<&bpmp TEGRA234_CLK_SPPLL0_VCO>,
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<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTPN>,
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<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTA>,
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<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTB>,
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<&bpmp TEGRA234_CLK_SPPLL0_DIV10>,
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<&bpmp TEGRA234_CLK_SPPLL0_DIV25>,
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<&bpmp TEGRA234_CLK_SPPLL0_DIV27PN>,
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<&bpmp TEGRA234_CLK_SPPLL1_VCO>,
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<&bpmp TEGRA234_CLK_SPPLL1_CLKOUTPN>,
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<&bpmp TEGRA234_CLK_SPPLL1_DIV27PN>,
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<&bpmp TEGRA234_CLK_VPLL0_REF>,
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<&bpmp TEGRA234_CLK_VPLL0>,
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<&bpmp TEGRA234_CLK_VPLL1>,
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<&bpmp TEGRA234_CLK_NVDISPLAY_P0_REF>,
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<&bpmp TEGRA234_CLK_RG0>,
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<&bpmp TEGRA234_CLK_RG1>,
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<&bpmp TEGRA234_CLK_DISPPLL>,
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<&bpmp TEGRA234_CLK_DISPHUBPLL>,
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<&bpmp TEGRA234_CLK_DSI_LP>,
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<&bpmp TEGRA234_CLK_DSI_CORE>,
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<&bpmp TEGRA234_CLK_DSI_PIXEL>,
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<&bpmp TEGRA234_CLK_PRE_SOR0>,
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<&bpmp TEGRA234_CLK_PRE_SOR1>,
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<&bpmp TEGRA234_CLK_DP_LINK_REF>,
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<&bpmp TEGRA234_CLK_SOR_LINKA_INPUT>,
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<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO>,
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<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO_M>,
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<&bpmp TEGRA234_CLK_RG0_M>,
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<&bpmp TEGRA234_CLK_RG1_M>,
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<&bpmp TEGRA234_CLK_SOR0_M>,
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<&bpmp TEGRA234_CLK_SOR1_M>,
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<&bpmp TEGRA234_CLK_PLLHUB>,
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<&bpmp TEGRA234_CLK_SOR0>,
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<&bpmp TEGRA234_CLK_SOR1>,
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<&bpmp TEGRA234_CLK_SOR_PAD_INPUT>,
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<&bpmp TEGRA234_CLK_PRE_SF0>,
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<&bpmp TEGRA234_CLK_SF0>,
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<&bpmp TEGRA234_CLK_SF1>,
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<&bpmp TEGRA234_CLK_DSI_PAD_INPUT>,
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<&bpmp TEGRA234_CLK_PRE_SOR0_REF>,
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<&bpmp TEGRA234_CLK_PRE_SOR1_REF>,
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<&bpmp TEGRA234_CLK_SOR0_PLL_REF>,
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<&bpmp TEGRA234_CLK_SOR1_PLL_REF>,
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<&bpmp TEGRA234_CLK_SOR0_REF>,
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<&bpmp TEGRA234_CLK_SOR1_REF>,
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<&bpmp TEGRA234_CLK_OSC>,
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<&bpmp TEGRA234_CLK_DSC>,
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<&bpmp TEGRA234_CLK_MAUD>,
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<&bpmp TEGRA234_CLK_AZA_2XBIT>,
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<&bpmp TEGRA234_CLK_AZA_BIT>,
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<&bpmp TEGRA234_CLK_MIPI_CAL>,
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<&bpmp TEGRA234_CLK_UART_FST_MIPI_CAL>,
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<&bpmp TEGRA234_CLK_SOR0_DIV>;
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clock-names = "nvdisplayhub_clk",
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"nvdisplay_disp_clk",
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"nvdisplay_p0_clk",
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"nvdisplay_p1_clk",
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"dpaux0_clk",
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"fuse_clk",
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"dsipll_vco_clk",
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"dsipll_clkoutpn_clk",
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"dsipll_clkouta_clk",
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"sppll0_vco_clk",
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"sppll0_clkoutpn_clk",
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"sppll0_clkouta_clk",
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"sppll0_clkoutb_clk",
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"sppll0_div10_clk",
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"sppll0_div25_clk",
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"sppll0_div27_clk",
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"sppll1_vco_clk",
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"sppll1_clkoutpn_clk",
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"sppll1_div27_clk",
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"vpll0_ref_clk",
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"vpll0_clk",
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"vpll1_clk",
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"nvdisplay_p0_ref_clk",
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"rg0_clk",
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"rg1_clk",
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"disppll_clk",
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"disphubpll_clk",
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"dsi_lp_clk",
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"dsi_core_clk",
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"dsi_pixel_clk",
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"pre_sor0_clk",
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"pre_sor1_clk",
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"dp_link_ref_clk",
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"sor_linka_input_clk",
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"sor_linka_afifo_clk",
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"sor_linka_afifo_m_clk",
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"rg0_m_clk",
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"rg1_m_clk",
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"sor0_m_clk",
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"sor1_m_clk",
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"pllhub_clk",
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"sor0_clk",
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"sor1_clk",
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"sor_pad_input_clk",
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"pre_sf0_clk",
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"sf0_clk",
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"sf1_clk",
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"dsi_pad_input_clk",
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"pre_sor0_ref_clk",
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"pre_sor1_ref_clk",
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"sor0_ref_pll_clk",
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"sor1_ref_pll_clk",
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"sor0_ref_clk",
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"sor1_ref_clk",
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"osc_clk",
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"dsc_clk",
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"maud_clk",
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"aza_2xbit_clk",
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"aza_bit_clk",
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"mipi_cal_clk",
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"uart_fst_mipi_cal_clk",
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"sor0_div_clk";
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resets = <&bpmp TEGRA234_RESET_NVDISPLAY>,
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<&bpmp TEGRA234_RESET_DPAUX>,
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<&bpmp TEGRA234_RESET_DSI_CORE>,
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<&bpmp TEGRA234_RESET_MIPI_CAL>;
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reset-names = "nvdisplay_reset",
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"dpaux0_reset",
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"dsi_core_reset",
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"mipi_cal_reset";
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status = "disabled";
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memory-region = <&fb0_reserved>;
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nvidia,disp-sw-soc-chip-id = <0x2350>;
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#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
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interconnect-names = "dma-mem", "read-1";
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#endif
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iommus = <&smmu_iso TEGRA234_SID_ISO_NVDISPLAY>;
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non-coherent;
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nvdisplay-niso {
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compatible = "nvidia,tegra234-display-niso";
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iommus = <&smmu_niso0 TEGRA234_SID_NVDISPLAY>;
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dma-coherent;
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};
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};
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};
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