mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
2d0af855ad
Enable FSI multi core support to communicate using CCPLEX fsicom demo
apps. It adds following to enable:
- add top2 hsp mailbox 5 and 4 for core 1 usage
- add FSI_CPU1 stream id for core 1 memory map in AST and SMMU
- new node per FSI core per SMMU instance
Bug 4243457
Change-Id: Id66c060d5daa1ca6458e3cbeee81dafc88904560
Signed-off-by: Dipen Patel <dipenp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2977860
(cherry picked from commit 4e450ca886 in
dev-main)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2995454
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
144 lines
4.3 KiB
Devicetree
144 lines
4.3 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/memory/tegra234-mc.h>
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/ {
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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fsicom_resv: reservation-fsicom {
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iommu-addresses = <&fsicom_client 0x0 0x0 0x0 0xf0000000>,
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<&fsicom_client 0x0 0xf1000000 0xffffffff 0x0effffff>;
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};
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fsicom_resv_inst1: reservation-fsicom_inst1 {
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iommu-addresses = <&fsicom_client_inst1 0x0 0x0 0x0 0xf0000000>,
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<&fsicom_client_inst1 0x0 0xf1000000 0xffffffff 0x0effffff>;
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};
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};
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fsicom_client: fsicom_client {
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compatible = "nvidia,tegra234-fsicom-client";
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#if TEGRA_HSP_DT_VERSION >= DT_VERSION_2
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mboxes =
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<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(2)>,
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<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(1)>,
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<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(5)>,
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<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(4)>;
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#else
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mboxes =
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<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(2)>,
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<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_RX(1)>,
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<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(5)>,
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<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_RX(4)>;
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#endif
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mbox-names = "fsi-tx-cpu0", "fsi-rx-cpu0", "fsi-tx-cpu1", "fsi-rx-cpu1";
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iommus = <&smmu_niso1 TEGRA234_SID_NISO1_FSI_CPU0>;
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memory-region = <&fsicom_resv>;
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dma-coherent;
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#if defined(ENABLE_FSI) && !defined(ENABLE_MODS_CONFIG)
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enable-deinit-notify;
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#endif
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smmu_inst = <0>;
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max_fsi_core=<1>; /*Value 1 <-> core 0, value 2 <-> core0,1*/
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status = "disabled";
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};
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fsicom_client_inst1: fsicom_client_inst1 {
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compatible = "nvidia,tegra234-fsicom-client";
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iommus = <&smmu_niso1 TEGRA234_SID_NISO1_FSI_CPU1>;
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memory-region = <&fsicom_resv_inst1>;
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dma-coherent;
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smmu_inst = <1>;
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status = "okay";
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};
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safetyservices_epl_client@110000 {
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compatible = "nvidia,tegra234-epl-client";
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#if TEGRA_HSP_DT_VERSION >= DT_VERSION_2
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mboxes =
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<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(0)>;
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#else
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mboxes =
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<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(0)>;
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#endif
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mbox-names = "epl-tx";
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reg = <0x0 0x00110000 0x0 0x4>,
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<0x0 0x00110004 0x0 0x4>,
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<0x0 0x00120000 0x0 0x4>,
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<0x0 0x00120004 0x0 0x4>,
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<0x0 0x00130000 0x0 0x4>,
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<0x0 0x00130004 0x0 0x4>,
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<0x0 0x00140000 0x0 0x4>,
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<0x0 0x00140004 0x0 0x4>,
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<0x0 0x00150000 0x0 0x4>,
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<0x0 0x00150004 0x0 0x4>,
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<0x0 0x024e0038 0x0 0x4>;
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/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR0_SW_ERR_CODE_0 */
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client-misc-sw-generic-err0 = "fsicom_client";
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/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR1_SW_ERR_CODE_0 */
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client-misc-sw-generic-err1 = "gk20b";
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/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR3_SW_ERR_CODE_0 */
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client-misc-sw-generic-err3 = "gk20d";
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/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR4_SW_ERR_CODE_0 */
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client-misc-sw-generic-err4 = "gk20e";
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#if defined(ENABLE_FSI) && !defined(ENABLE_MODS_CONFIG)
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enable-deinit-notify;
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#endif
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status = "disabled";
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};
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FsiComIvc {
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compatible = "nvidia,tegra-fsicom-channels";
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status = "disabled";
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nChannel=<7>;
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channel_0{
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frame-count = <4>;
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frame-size = <1024>;
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core-id = <0>;
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NvSciCh = "nvfsicom_EPD";
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};
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channel_1{
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frame-count = <30>;
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frame-size = <64>;
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core-id = <0>;
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NvSciCh = "nvfsicom_CcplexApp";
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};
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channel_2{
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frame-count = <4>;
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frame-size = <64>;
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core-id = <0>;
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NvSciCh = "nvfsicom_CcplexApp_state_change";
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};
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channel_3{
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frame-count = <4>;
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frame-size = <64>;
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core-id = <0>;
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NvSciCh = "nvfsicom_app1";
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};
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channel_4{
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frame-count = <2>;
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frame-size = <64>;
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core-id = <1>;
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NvSciCh = "nvfsicom_app2";
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};
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channel_5{
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frame-count = <4>;
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frame-size = <64>;
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core-id = <0>;
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NvSciCh = "nvfsicom_appGR";
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};
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channel_6{
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frame-count = <4>;
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frame-size = <10240>;
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core-id = <0>;
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};
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};
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FsiComClientChConfigEpd {
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compatible = "nvidia,tegra-fsicom-EPD";
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status = "disabled";
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channelid_list = <0>;
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};
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}; |