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common: overlay: Add common overlay for Jetson

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Add the following device-tree overlay templates for the Jetson
platforms.

1. ADAFRUIT SPH0645LM4H (I2S MEMS Microphone)
2. FE-PI Audio Z V2 (SGTL5000 Audio Codec)

Note that these templates cannot be compiled as-is because they include
definitions that are defined in the corresponding
'dt-bindings/platform/jetson/<board>.h'. Therefore, to use these
templates they need to be compiled along with the appropriate include
file.

These have been created to avoid duplicating nodes that are common to
all Jetson platforms for using these add-on modules.

Bug 2414131

Change-Id: I60b29bb72fdd206786fd76cd1676ed6d6f3c9f1b
Signed-off-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202471
(cherry picked from commit 3ca13ed86364fe2b606e470870ffa778f36a03c9)
Reviewed-on: https://git-master.nvidia.com/r/2217432
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Jonathan Hunter
2019-09-11 14:46:01 +01:00
committed by Laxman Dewangan
parent bf6151adea
commit 020a01a620
2 changed files with 159 additions and 0 deletions
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49
overlay/jetson-adafruit-sph0645lm4h.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Jetson Device-tree overlay for Adafruit I2S MEMS Microphone Breakout
* (SPH0645LM4H).
*
* Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved.
*
*/
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
/ {
overlay-name = "Adafruit SPH0645LM4H";
compatible = JETSON_COMPATIBLE;
fragment@0 {
target = <&pinmux>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&hdr40_pinmux>;
hdr40_pinmux: header-40pin-pinmux {
pin12 {
nvidia,pins = HDR40_PIN12;
nvidia,function = HDR40_I2S;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pin35 {
nvidia,pins = HDR40_PIN35;
nvidia,function = HDR40_I2S;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pin38 {
nvidia,pins = HDR40_PIN38;
nvidia,function = HDR40_I2S;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
};
};
};

110
overlay/jetson-fe-pi-audio-z-v2.dts Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Jetson Device-tree overlay for FE-PI Audio Z V2.
*
* Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved.
*
*/
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
/ {
overlay-name = "FE-PI Audio Z V2";
compatible = JETSON_COMPATIBLE;
fragment@0 {
target-path = "/";
__overlay__ {
clocks {
sgtl5000_mclk: sgtl5000_mclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
clock-output-names = "sgtl5000-mclk";
status = "okay";
};
};
};
};
fragment@1 {
target = <&hdr40_i2c1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
sgtl5000: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&sgtl5000_mclk>;
micbias-resistor-k-ohms = <2>;
micbias-voltage-m-volts = <3000>;
VDDA-supply = <&hdr40_vdd_3v3>;
VDDIO-supply = <&hdr40_vdd_3v3>;
status = "okay";
};
};
};
fragment@2 {
target = <&tegra_sound>;
__overlay__ {
nvidia,audio-routing =
"x Headphone", "x HP_OUT",
"x MIC_IN", "x Mic";
};
};
fragment@3 {
target = <&hdr40_snd_link_i2s>;
__overlay__ {
link-name = "fe-pi-audio-z-v2";
codec-dai = <&sgtl5000>;
codec-dai-name = "sgtl5000";
bitclock-master;
frame-master;
};
};
fragment@4 {
target = <&pinmux>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&hdr40_pinmux>;
hdr40_pinmux: header-40pin-pinmux {
pin12 {
nvidia,pins = HDR40_PIN12;
nvidia,function = HDR40_I2S;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pin35 {
nvidia,pins = HDR40_PIN35;
nvidia,function = HDR40_I2S;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pin38 {
nvidia,pins = HDR40_PIN38;
nvidia,function = HDR40_I2S;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pin40 {
nvidia,pins = HDR40_PIN40;
nvidia,function = HDR40_I2S;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
};
};
};