mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/tegra-public-dts.git
synced 2025-12-22 09:11:55 +03:00
8ba5d53ef1
Rename all common jetson audio files to have jetson-audio-* to have the easily identification. Change-Id: I69248b0864598c2a0d17f99fc7b3c1b123e501b3 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/tegra-public-dts/+/2926979 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-by: Sameer Pujar <spujar@nvidia.com>
97 lines
2.4 KiB
Devicetree
97 lines
2.4 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Jetson Device-tree overlay for MCP251x CAN Controller.
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*/
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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/ {
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overlay-name = "MCP251x CAN Controller";
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jetson-header-name = "Jetson 40pin Header";
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compatible = JETSON_COMPATIBLE;
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fragment@0 {
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target-path = "/";
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__overlay__ {
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clocks {
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can_clock: can_clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <20000000>;
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clock-accuracy = <100>;
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};
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};
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};
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};
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fragment@1 {
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target = <&hdr40_spi1>;
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__overlay__ {
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spi@0 {
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compatible = "microchip,mcp2515";
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reg = <0x0>;
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spi-max-frequency = <10000000>;
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x7>;
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clocks = <&can_clock>;
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interrupt-parent = <&gpio>;
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interrupts = <HDR40_PIN31_GPIO 0x1>;
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controller-data {
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nvidia,cs-setup-clk-count = <0x1e>;
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nvidia,cs-hold-clk-count = <0x1e>;
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nvidia,rx-clk-tap-delay = <0x1f>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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};
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};
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fragment@2 {
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target = <&pinmux>;
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__overlay__ {
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pinctrl-names = "default";
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pinctrl-0 = <&jetson_io_pinmux>;
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jetson_io_pinmux: exp-header-pinmux {
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hdr40-pin19 {
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nvidia,pins = HDR40_PIN19;
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nvidia,function = HDR40_SPI;
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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hdr40-pin21 {
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nvidia,pins = HDR40_PIN21;
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nvidia,function = HDR40_SPI;
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin23 {
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nvidia,pins = HDR40_PIN23;
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nvidia,function = HDR40_SPI;
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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hdr40-pin24 {
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nvidia,pins = HDR40_PIN24;
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nvidia,function = HDR40_SPI;
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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hdr40-pin26 {
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nvidia,pins = HDR40_PIN26;
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nvidia,function = HDR40_SPI;
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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};
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};
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};
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};
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