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tegra: hwpm: t234: add generated hw headers

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- Generate HWPM hw headers using register generator tool.
- Add required hw headers to include/hw/ path
- Update driver code to replace static hw defines with hw header
definitions.
- Remove unused static hw defines.

THWPM-39

Change-Id: I57566d51657bb6b22c4b581acd257f1871438adf
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2552741
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2021-07-01 13:04:12 -07:00
committed by mobile promotions
parent 78465d56ca
commit 0cb6f6b48f
7 changed files with 814 additions and 742 deletions
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165
include/hw/t234/hw_addr_map_soc_hwpm.h Normal file
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/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef TEGRA_HW_ADDR_MAP_SOC_HWPM_H
#define TEGRA_HW_ADDR_MAP_SOC_HWPM_H
#define addr_map_rpg_pm_base_r() (0x0f100000U)
#define addr_map_rpg_pm_limit_r() (0x0f149fffU)
#define addr_map_pma_base_r() (0x0f14a000U)
#define addr_map_rtr_base_r() (0x0f14d000U)
#define addr_map_disp_base_r() (0x13800000U)
#define addr_map_disp_limit_r() (0x138effffU)
#define addr_map_vi_thi_base_r() (0x15f00000U)
#define addr_map_vi_thi_limit_r() (0x15ffffffU)
#define addr_map_vi2_thi_base_r() (0x14f00000U)
#define addr_map_vi2_thi_limit_r() (0x14ffffffU)
#define addr_map_vic_base_r() (0x15340000U)
#define addr_map_vic_limit_r() (0x1537ffffU)
#define addr_map_nvdec_base_r() (0x15480000U)
#define addr_map_nvdec_limit_r() (0x154bffffU)
#define addr_map_nvenc_base_r() (0x154c0000U)
#define addr_map_nvenc_limit_r() (0x154fffffU)
#define addr_map_ofa_base_r() (0x15a50000U)
#define addr_map_ofa_limit_r() (0x15a5ffffU)
#define addr_map_isp_thi_base_r() (0x14b00000U)
#define addr_map_isp_thi_limit_r() (0x14bfffffU)
#define addr_map_pcie_c0_ctl_base_r() (0x14180000U)
#define addr_map_pcie_c0_ctl_limit_r() (0x1419ffffU)
#define addr_map_pcie_c1_ctl_base_r() (0x14100000U)
#define addr_map_pcie_c1_ctl_limit_r() (0x1411ffffU)
#define addr_map_pcie_c2_ctl_base_r() (0x14120000U)
#define addr_map_pcie_c2_ctl_limit_r() (0x1413ffffU)
#define addr_map_pcie_c3_ctl_base_r() (0x14140000U)
#define addr_map_pcie_c3_ctl_limit_r() (0x1415ffffU)
#define addr_map_pcie_c4_ctl_base_r() (0x14160000U)
#define addr_map_pcie_c4_ctl_limit_r() (0x1417ffffU)
#define addr_map_pcie_c5_ctl_base_r() (0x141a0000U)
#define addr_map_pcie_c5_ctl_limit_r() (0x141bffffU)
#define addr_map_pcie_c6_ctl_base_r() (0x141c0000U)
#define addr_map_pcie_c6_ctl_limit_r() (0x141dffffU)
#define addr_map_pcie_c7_ctl_base_r() (0x141e0000U)
#define addr_map_pcie_c7_ctl_limit_r() (0x141fffffU)
#define addr_map_pcie_c8_ctl_base_r() (0x140a0000U)
#define addr_map_pcie_c8_ctl_limit_r() (0x140bffffU)
#define addr_map_pcie_c9_ctl_base_r() (0x140c0000U)
#define addr_map_pcie_c9_ctl_limit_r() (0x140dffffU)
#define addr_map_pcie_c10_ctl_base_r() (0x140e0000U)
#define addr_map_pcie_c10_ctl_limit_r() (0x140fffffU)
#define addr_map_pva0_pm_base_r() (0x16200000U)
#define addr_map_pva0_pm_limit_r() (0x1620ffffU)
#define addr_map_nvdla0_base_r() (0x15880000U)
#define addr_map_nvdla0_limit_r() (0x158bffffU)
#define addr_map_nvdla1_base_r() (0x158c0000U)
#define addr_map_nvdla1_limit_r() (0x158fffffU)
#define addr_map_mgbe0_base_r() (0x06800000U)
#define addr_map_mgbe0_limit_r() (0x068fffffU)
#define addr_map_mgbe1_base_r() (0x06900000U)
#define addr_map_mgbe1_limit_r() (0x069fffffU)
#define addr_map_mgbe2_base_r() (0x06a00000U)
#define addr_map_mgbe2_limit_r() (0x06afffffU)
#define addr_map_mgbe3_base_r() (0x06b00000U)
#define addr_map_mgbe3_limit_r() (0x06bfffffU)
#define addr_map_mcb_base_r() (0x02c10000U)
#define addr_map_mcb_limit_r() (0x02c1ffffU)
#define addr_map_mc0_base_r() (0x02c20000U)
#define addr_map_mc0_limit_r() (0x02c2ffffU)
#define addr_map_mc1_base_r() (0x02c30000U)
#define addr_map_mc1_limit_r() (0x02c3ffffU)
#define addr_map_mc2_base_r() (0x02c40000U)
#define addr_map_mc2_limit_r() (0x02c4ffffU)
#define addr_map_mc3_base_r() (0x02c50000U)
#define addr_map_mc3_limit_r() (0x02c5ffffU)
#define addr_map_mc4_base_r() (0x02b80000U)
#define addr_map_mc4_limit_r() (0x02b8ffffU)
#define addr_map_mc5_base_r() (0x02b90000U)
#define addr_map_mc5_limit_r() (0x02b9ffffU)
#define addr_map_mc6_base_r() (0x02ba0000U)
#define addr_map_mc6_limit_r() (0x02baffffU)
#define addr_map_mc7_base_r() (0x02bb0000U)
#define addr_map_mc7_limit_r() (0x02bbffffU)
#define addr_map_mc8_base_r() (0x01700000U)
#define addr_map_mc8_limit_r() (0x0170ffffU)
#define addr_map_mc9_base_r() (0x01710000U)
#define addr_map_mc9_limit_r() (0x0171ffffU)
#define addr_map_mc10_base_r() (0x01720000U)
#define addr_map_mc10_limit_r() (0x0172ffffU)
#define addr_map_mc11_base_r() (0x01730000U)
#define addr_map_mc11_limit_r() (0x0173ffffU)
#define addr_map_mc12_base_r() (0x01740000U)
#define addr_map_mc12_limit_r() (0x0174ffffU)
#define addr_map_mc13_base_r() (0x01750000U)
#define addr_map_mc13_limit_r() (0x0175ffffU)
#define addr_map_mc14_base_r() (0x01760000U)
#define addr_map_mc14_limit_r() (0x0176ffffU)
#define addr_map_mc15_base_r() (0x01770000U)
#define addr_map_mc15_limit_r() (0x0177ffffU)
#define addr_map_mss_nvlink_1_base_r() (0x01f20000U)
#define addr_map_mss_nvlink_1_limit_r() (0x01f3ffffU)
#define addr_map_mss_nvlink_2_base_r() (0x01f40000U)
#define addr_map_mss_nvlink_2_limit_r() (0x01f5ffffU)
#define addr_map_mss_nvlink_3_base_r() (0x01f60000U)
#define addr_map_mss_nvlink_3_limit_r() (0x01f7ffffU)
#define addr_map_mss_nvlink_4_base_r() (0x01f80000U)
#define addr_map_mss_nvlink_4_limit_r() (0x01f9ffffU)
#define addr_map_mss_nvlink_5_base_r() (0x01fa0000U)
#define addr_map_mss_nvlink_5_limit_r() (0x01fbffffU)
#define addr_map_mss_nvlink_6_base_r() (0x01fc0000U)
#define addr_map_mss_nvlink_6_limit_r() (0x01fdffffU)
#define addr_map_mss_nvlink_7_base_r() (0x01fe0000U)
#define addr_map_mss_nvlink_7_limit_r() (0x01ffffffU)
#define addr_map_mss_nvlink_8_base_r() (0x01e00000U)
#define addr_map_mss_nvlink_8_limit_r() (0x01e1ffffU)
#endif

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include/hw/t234/hw_pmasys_soc_hwpm.h Normal file
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/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef TEGRA_HW_PMASYS_SOC_HWPM_H
#define TEGRA_HW_PMASYS_SOC_HWPM_H
#define pmasys_cg2_r() (0x0f14a044U)
#define pmasys_cg2_slcg_f(v) (((v) & 0x1U) << 0U)
#define pmasys_cg2_slcg_m() (0x1U << 0U)
#define pmasys_cg2_slcg_enabled_v() (0x00000000U)
#define pmasys_cg2_slcg_enabled_f() (0x0U)
#define pmasys_cg2_slcg_disabled_v() (0x00000001U)
#define pmasys_cg2_slcg_disabled_f() (0x1U)
#define pmasys_controlb_r() (0x0f14a070U)
#define pmasys_controlb_coalesce_timeout_cycles_f(v) (((v) & 0x7U) << 4U)
#define pmasys_controlb_coalesce_timeout_cycles_m() (0x7U << 4U)
#define pmasys_controlb_coalesce_timeout_cycles__prod_f() (0x40U)
#define pmasys_channel_status_secure_r(i)\
(0x0f14a610U + ((i)*384U))
#define pmasys_channel_status_secure_membuf_status_f(v) (((v) & 0x1U) << 0U)
#define pmasys_channel_status_secure_membuf_status_m() (0x1U << 0U)
#define pmasys_channel_status_secure_membuf_status_v(r) (((r) >> 0U) & 0x1U)
#define pmasys_channel_status_secure_membuf_status_init_v() (0x00000000U)
#define pmasys_channel_status_secure_membuf_status_overflowed_v() (0x00000001U)
#define pmasys_channel_control_user_r(i)\
(0x0f14a620U + ((i)*384U))
#define pmasys_channel_control_user_stream_f(v) (((v) & 0x1U) << 0U)
#define pmasys_channel_control_user_stream_m() (0x1U << 0U)
#define pmasys_channel_control_user_stream_disable_v() (0x00000000U)
#define pmasys_channel_control_user_stream_disable_f() (0x0U)
#define pmasys_channel_control_user_stream_enable_v() (0x00000001U)
#define pmasys_channel_control_user_update_bytes_f(v) (((v) & 0x1U) << 31U)
#define pmasys_channel_control_user_update_bytes_m() (0x1U << 31U)
#define pmasys_channel_control_user_update_bytes_doit_v() (0x00000001U)
#define pmasys_channel_control_user_update_bytes_doit_f() (0x80000000U)
#define pmasys_channel_mem_bump_r(i)\
(0x0f14a624U + ((i)*4U))
#define pmasys_channel_mem_block_r(i)\
(0x0f14a638U + ((i)*4U))
#define pmasys_channel_mem_block__size_1_v() (0x00000001U)
#define pmasys_channel_mem_block_ptr_f(v) (((v) & 0x3fffffffU) << 0U)
#define pmasys_channel_mem_block_ptr_m() (0x3fffffffU << 0U)
#define pmasys_channel_mem_block_base_f(v) (((v) & 0xfffffffU) << 0U)
#define pmasys_channel_mem_block_base_m() (0xfffffffU << 0U)
#define pmasys_channel_mem_block_target_f(v) (((v) & 0x3U) << 28U)
#define pmasys_channel_mem_block_target_m() (0x3U << 28U)
#define pmasys_channel_mem_block_target_lfb_v() (0x00000000U)
#define pmasys_channel_mem_block_target_sys_coh_v() (0x00000002U)
#define pmasys_channel_mem_block_target_sys_ncoh_v() (0x00000003U)
#define pmasys_channel_mem_block_valid_f(v) (((v) & 0x1U) << 31U)
#define pmasys_channel_mem_block_valid_m() (0x1U << 31U)
#define pmasys_channel_mem_block_valid_false_v() (0x00000000U)
#define pmasys_channel_mem_block_valid_true_v() (0x00000001U)
#define pmasys_channel_config_user_r(i)\
(0x0f14a640U + ((i)*384U))
#define pmasys_channel_config_user_coalesce_timeout_cycles_f(v)\
(((v) & 0x7U) << 4U)
#define pmasys_channel_config_user_coalesce_timeout_cycles_m() (0x7U << 4U)
#define pmasys_channel_config_user_coalesce_timeout_cycles__prod_v()\
(0x00000004U)
#define pmasys_channel_config_user_coalesce_timeout_cycles__prod_f() (0x40U)
#define pmasys_channel_outbase_r(i)\
(0x0f14a644U + ((i)*4U))
#define pmasys_channel_outbase_ptr_f(v) (((v) & 0x7ffffffU) << 5U)
#define pmasys_channel_outbase_ptr_m() (0x7ffffffU << 5U)
#define pmasys_channel_outbase_ptr_v(r) (((r) >> 5U) & 0x7ffffffU)
#define pmasys_channel_outbaseupper_r(i)\
(0x0f14a648U + ((i)*4U))
#define pmasys_channel_outbaseupper_ptr_f(v) (((v) & 0xffU) << 0U)
#define pmasys_channel_outbaseupper_ptr_m() (0xffU << 0U)
#define pmasys_channel_outbaseupper_ptr_v(r) (((r) >> 0U) & 0xffU)
#define pmasys_channel_outsize_r(i)\
(0x0f14a64cU + ((i)*4U))
#define pmasys_channel_outsize_numbytes_f(v) (((v) & 0x7ffffffU) << 5U)
#define pmasys_channel_outsize_numbytes_m() (0x7ffffffU << 5U)
#define pmasys_channel_mem_head_r(i)\
(0x0f14a650U + ((i)*4U))
#define pmasys_channel_mem_bytes_addr_r(i)\
(0x0f14a658U + ((i)*4U))
#define pmasys_channel_mem_bytes_addr_ptr_f(v) (((v) & 0x3fffffffU) << 2U)
#define pmasys_channel_mem_bytes_addr_ptr_m() (0x3fffffffU << 2U)
#define pmasys_trigger_config_user_r(i)\
(0x0f14a694U + ((i)*384U))
#define pmasys_trigger_config_user_pma_pulse_f(v) (((v) & 0x1U) << 0U)
#define pmasys_trigger_config_user_pma_pulse_m() (0x1U << 0U)
#define pmasys_trigger_config_user_pma_pulse_disable_v() (0x00000000U)
#define pmasys_trigger_config_user_pma_pulse_disable_f() (0x0U)
#define pmasys_trigger_config_user_pma_pulse_enable_v() (0x00000001U)
#define pmasys_trigger_config_user_record_stream_f(v) (((v) & 0x1U) << 6U)
#define pmasys_trigger_config_user_record_stream_m() (0x1U << 6U)
#define pmasys_trigger_config_user_record_stream_disable_v() (0x00000000U)
#define pmasys_trigger_config_user_record_stream_disable_f() (0x0U)
#define pmasys_trigger_config_user_record_stream_enable_v() (0x00000001U)
#define pmasys_enginestatus_r() (0x0f14a75cU)
#define pmasys_enginestatus_status_s() (3U)
#define pmasys_enginestatus_status_f(v) (((v) & 0x7U) << 0U)
#define pmasys_enginestatus_status_m() (0x7U << 0U)
#define pmasys_enginestatus_status_v(r) (((r) >> 0U) & 0x7U)
#define pmasys_enginestatus_status_w() (0U)
#define pmasys_enginestatus_status_empty_v() (0x00000000U)
#define pmasys_enginestatus_status_empty_f() (0x0U)
#define pmasys_enginestatus_status_active_v() (0x00000001U)
#define pmasys_enginestatus_status_paused_v() (0x00000002U)
#define pmasys_enginestatus_status_quiescent_v() (0x00000003U)
#define pmasys_enginestatus_status_stalled_v() (0x00000005U)
#define pmasys_enginestatus_status_faulted_v() (0x00000006U)
#define pmasys_enginestatus_status_halted_v() (0x00000007U)
#define pmasys_enginestatus_rbufempty_s() (1U)
#define pmasys_enginestatus_rbufempty_f(v) (((v) & 0x1U) << 4U)
#define pmasys_enginestatus_rbufempty_m() (0x1U << 4U)
#define pmasys_enginestatus_rbufempty_v(r) (((r) >> 4U) & 0x1U)
#define pmasys_enginestatus_rbufempty_w() (0U)
#define pmasys_enginestatus_rbufempty_empty_v() (0x00000001U)
#define pmasys_enginestatus_rbufempty_empty_f() (0x10U)
#define pmasys_enginestatus_mbu_status_f(v) (((v) & 0x3U) << 5U)
#define pmasys_enginestatus_mbu_status_m() (0x3U << 5U)
#define pmasys_enginestatus_mbu_status_idle_v() (0x00000000U)
#define pmasys_enginestatus_mbu_status_busy_v() (0x00000001U)
#define pmasys_enginestatus_mbu_status_pending_v() (0x00000002U)
#define pmasys_sys_trigger_start_mask_r() (0x0f14a66cU)
#define pmasys_sys_trigger_start_maskb_r() (0x0f14a670U)
#define pmasys_sys_trigger_stop_mask_r() (0x0f14a684U)
#define pmasys_sys_trigger_stop_maskb_r() (0x0f14a688U)
#endif

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include/hw/t234/hw_pmmsys_soc_hwpm.h Normal file
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/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Function/Macro naming determines intended use:
*
* <x>_r(void) : Returns the offset for register <x>.
*
* <x>_o(void) : Returns the offset for element <x>.
*
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
*
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
*
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
* and masked to place it at field <y> of register <x>. This value
* can be |'d with others to produce a full register value for
* register <x>.
*
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
* value can be ~'d and then &'d to clear the value of field <y> for
* register <x>.
*
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
* to place it at field <y> of register <x>. This value can be |'d
* with others to produce a full register value for <x>.
*
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
* <x> value 'r' after being shifted to place its LSB at bit 0.
* This value is suitable for direct comparison with other unshifted
* values appropriate for use in field <y> of register <x>.
*
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
* field <y> of register <x>. This value is suitable for direct
* comparison with unshifted values appropriate for use in field <y>
* of register <x>.
*/
#ifndef TEGRA_HW_PMMSYS_SOC_HWPM_H
#define TEGRA_HW_PMMSYS_SOC_HWPM_H
#define pmmsys_perdomain_offset_v() (0x00001000U)
#define pmmsys_control_r(i)\
(0x0f10009cU + ((i)*4096U))
#define pmmsys_control_mode_f(v) (((v) & 0x7U) << 0U)
#define pmmsys_control_mode_m() (0x7U << 0U)
#define pmmsys_control_mode_disable_v() (0x00000000U)
#define pmmsys_control_mode_disable_f() (0x0U)
#define pmmsys_control_mode_a_v() (0x00000001U)
#define pmmsys_control_mode_b_v() (0x00000002U)
#define pmmsys_control_mode_c_v() (0x00000003U)
#define pmmsys_control_mode_e_v() (0x00000005U)
#define pmmsys_control_mode_null_v() (0x00000007U)
#define pmmsys_sys0_enginestatus_r(i)\
(0x0f1000c8U + ((i)*4096U))
#define pmmsys_sys0_enginestatus_enable_f(v) (((v) & 0x1U) << 8U)
#define pmmsys_sys0_enginestatus_enable_m() (0x1U << 8U)
#define pmmsys_sys0_enginestatus_enable_masked_v() (0x00000000U)
#define pmmsys_sys0_enginestatus_enable_out_v() (0x00000001U)
#define pmmsys_sys0_enginestatus_enable_out_f() (0x100U)
#define pmmsys_sys0router_enginestatus_r() (0x0f14d010U)
#define pmmsys_sys0router_enginestatus_status_f(v) (((v) & 0x7U) << 0U)
#define pmmsys_sys0router_enginestatus_status_m() (0x7U << 0U)
#define pmmsys_sys0router_enginestatus_status_v(r) (((r) >> 0U) & 0x7U)
#define pmmsys_sys0router_enginestatus_status_empty_v() (0x00000000U)
#define pmmsys_sys0router_enginestatus_status_active_v() (0x00000001U)
#define pmmsys_sys0router_enginestatus_status_paused_v() (0x00000002U)
#define pmmsys_sys0router_enginestatus_status_quiescent_v() (0x00000003U)
#define pmmsys_sys0router_enginestatus_status_stalled_v() (0x00000005U)
#define pmmsys_sys0router_enginestatus_status_faulted_v() (0x00000006U)
#define pmmsys_sys0router_enginestatus_status_halted_v() (0x00000007U)
#define pmmsys_sys0router_enginestatus_enable_f(v) (((v) & 0x1U) << 8U)
#define pmmsys_sys0router_enginestatus_enable_m() (0x1U << 8U)
#define pmmsys_sys0router_enginestatus_enable_masked_v() (0x00000000U)
#define pmmsys_sys0router_enginestatus_enable_out_v() (0x00000001U)
#define pmmsys_sys0router_perfmonstatus_r() (0x0f14d014U)
#define pmmsys_sys0router_perfmonstatus_merged_f(v) (((v) & 0x7U) << 0U)
#define pmmsys_sys0router_perfmonstatus_merged_m() (0x7U << 0U)
#define pmmsys_sys0router_perfmonstatus_merged_v(r) (((r) >> 0U) & 0x7U)
#define pmmsys_sys0router_cg2_r() (0x0f14d018U)
#define pmmsys_sys0router_cg2_slcg_f(v) (((v) & 0x3U) << 0U)
#define pmmsys_sys0router_cg2_slcg_m() (0x3U << 0U)
#define pmmsys_sys0router_cg2_slcg_enabled_v() (0x00000000U)
#define pmmsys_sys0router_cg2_slcg_enabled_f() (0x0U)
#define pmmsys_sys0router_cg2_slcg_disabled_v() (0x00000003U)
#define pmmsys_sys0router_cg2_slcg_disabled_f() (0x3U)
#endif

285
tegra-soc-hwpm-hw.h
View File

@@ -23,6 +23,10 @@
#include <linux/types.h>
#include "include/hw/t234/hw_addr_map_soc_hwpm.h"
#include "include/hw/t234/hw_pmasys_soc_hwpm.h"
#include "include/hw/t234/hw_pmmsys_soc_hwpm.h"
/* FIXME: Move enum to DT include file? */
enum tegra_soc_hwpm_dt_aperture {
TEGRA_SOC_HWPM_INVALID_DT = -1,
@@ -95,283 +99,8 @@ enum tegra_soc_hwpm_dt_aperture {
((idx) <= TEGRA_SOC_HWPM_LAST_PERFMON_DT))
/* RPG_PM Aperture */
/* FIXME: Use __SIZE_1 for handling per PERFMON registers? */
#define NV_ADDRESS_MAP_RPG_PM_BASE 0x0f100000
#define NV_ADDRESS_MAP_RPG_PM_LIMIT 0x0f149fff
#define NV_PERF_PMMSYS_PERDOMAIN_OFFSET 0x1000
#define PERFMON_BASE(ip_idx) (NV_ADDRESS_MAP_RPG_PM_BASE + \
((u32)(ip_idx)) * NV_PERF_PMMSYS_PERDOMAIN_OFFSET)
#define PERFMON_LIMIT(ip_idx) (PERFMON_BASE((ip_idx) + 1) - 1)
#define NV_PERF_PMMSYS_CONTROL 0x9C
#define NV_PERF_PMMSYS_CONTROL_MODE_SHIFT 0
#define NV_PERF_PMMSYS_CONTROL_MODE_MASK 0x00000007
#define NV_PERF_PMMSYS_CONTROL_MODE_DISABLE 0x00000000
#define NV_PERF_PMMSYS_CONTROL_MODE_A 0x00000001
#define NV_PERF_PMMSYS_CONTROL_MODE_B 0x00000002
#define NV_PERF_PMMSYS_CONTROL_MODE_C 0x00000003
#define NV_PERF_PMMSYS_CONTROL_MODE_E 0x00000005
#define NV_PERF_PMMSYS_CONTROL_MODE_NULL 0x00000007
#define NV_PERF_PMMSYS_SYS0_ENGINESTATUS 0xC8
#define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_ENABLE_SHIFT 8
#define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_ENABLE_MASK 0x00000100
#define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_ENABLE_MASKED 0x0
#define NV_PERF_PMMSYS_SYS0_ENGINESTATUS_ENABLE_OUT 0x1
/* PMA Aperture */
/* FIXME: Add __SIZE_1 logic for channels? */
#define NV_ADDRESS_MAP_PMA_BASE 0x0f14a000
#define NV_ADDRESS_MAP_PMA_LIMIT 0x0f14bfff
#define NV_PERF_PMASYS_CG2 0x44
#define NV_PERF_PMASYS_CG2_SLCG_SHIFT 0
/* FIXME: Use standard format for masks */
#define NV_PERF_PMASYS_CG2_SLCG_MASK 0x1
#define NV_PERF_PMASYS_CG2_SLCG_ENABLED 0x00000000
#define NV_PERF_PMASYS_CG2_SLCG_DISABLED 0x00000001
#define NV_PERF_PMASYS_CONTROLB 0x70
#define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES_SHIFT 4
#define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES_MASK 0x00000070
#define NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES__PROD 0x00000004
#define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE(i) (0x610+(i)*0x180)
#define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_CH0 NV_PERF_PMASYS_CHANNEL_STATUS_SECURE(0)
#define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_MEMBUF_STATUS_SHIFT 0
#define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_MEMBUF_STATUS_MASK 0x00000001
#define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_MEMBUF_STATUS_INIT 0x00000000
#define NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_MEMBUF_STATUS_OVERFLOWED 0x00000001
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER(i) (0x620+(i)*0x180)
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_CH0 NV_PERF_PMASYS_CHANNEL_CONTROL_USER(0)
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_STREAM_SHIFT 0
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_STREAM_MASK 0x00000001
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_STREAM_DISABLE 0x00000000
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_STREAM_ENABLE 0x00000001
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_UPDATE_BYTES_SHIFT 31
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_UPDATE_BYTES_MASK 0x80000000
#define NV_PERF_PMASYS_CHANNEL_CONTROL_USER_UPDATE_BYTES_DOIT 0x00000001
#define NV_PERF_PMASYS_CHANNEL_MEM_BUMP(i) (0x624+(i)*4)
#define NV_PERF_PMASYS_CHANNEL_MEM_BUMP_CH0 NV_PERF_PMASYS_CHANNEL_MEM_BUMP(0)
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK(i) (0x638+(i)*4)
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_CH0 NV_PERF_PMASYS_CHANNEL_MEM_BLOCK(0)
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_PTR_SHIFT 0
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_PTR_MASK 0x3fffffff
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_BASE_SHIFT 0
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_BASE_MASK 0xfffffff
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_TARGET_SHIFT 28
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_TARGET_MASK 0x30000000
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_TARGET_LFB 0x00000000
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_TARGET_SYS_COH 0x00000002
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_TARGET_SYS_NCOH 0x00000003
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_VALID_SHIFT 31
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_VALID_MASK 0x80000000
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_VALID_FALSE 0x00000000
#define NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_VALID_TRUE 0x00000001
#define NV_PERF_PMASYS_CHANNEL_CONFIG_USER(i) (0x640+(i)*0x180)
#define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_CH0 NV_PERF_PMASYS_CHANNEL_CONFIG_USER(0)
#define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES_SHIFT 4
#define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES_MASK 0x00000070
#define NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES__PROD 0x00000004
#define NV_PERF_PMASYS_CHANNEL_OUTBASE(i) (0x644+(i)*4)
#define NV_PERF_PMASYS_CHANNEL_OUTBASE_CH0 NV_PERF_PMASYS_CHANNEL_OUTBASE(0)
#define NV_PERF_PMASYS_CHANNEL_OUTBASE_PTR_SHIFT 5
#define NV_PERF_PMASYS_CHANNEL_OUTBASE_PTR_MASK 0xffffffe0
#define NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER(i) (0x648+(i)*4)
#define NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_CH0 NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER(0)
#define NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_PTR_SHIFT 0
#define NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_PTR_MASK 0x000000ff
#define NV_PERF_PMASYS_CHANNEL_OUTSIZE(i) (0x64C+(i)*4)
#define NV_PERF_PMASYS_CHANNEL_OUTSIZE_CH0 NV_PERF_PMASYS_CHANNEL_OUTSIZE(0)
#define NV_PERF_PMASYS_CHANNEL_OUTSIZE_NUMBYTES_SHIFT 5
#define NV_PERF_PMASYS_CHANNEL_OUTSIZE_NUMBYTES_MASK 0xffffffe0
#define NV_PERF_PMASYS_CHANNEL_MEM_HEAD(i) (0x650+(i)*4)
#define NV_PERF_PMASYS_CHANNEL_MEM_HEAD_CH0 NV_PERF_PMASYS_CHANNEL_MEM_HEAD(0)
#define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR(i) (0x658+(i)*4)
#define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_CH0 NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR(0)
#define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_PTR_SHIFT 2
#define NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_PTR_MASK 0xfffffffc
#define NV_PERF_PMASYS_SYS_TRIGGER_START_MASK 0x66C
#define NV_PERF_PMASYS_SYS_TRIGGER_START_MASKB 0x670
#define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK 0x684
#define NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASKB 0x688
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER(i) (0x694+(i)*0x180)
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_CH0 NV_PERF_PMASYS_TRIGGER_CONFIG_USER(0)
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_SHIFT 0
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_MASK 0x00000001
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_DISABLE 0x00000000
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_ENABLE 0x00000001
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RECORD_STREAM_SHIFT 6
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RECORD_STREAM_MASK 0x00000040
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RECORD_STREAM_DISABLE 0x00000000
#define NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RECORD_STREAM_ENABLE 0x00000001
#define NV_PERF_PMASYS_ENGINESTATUS 0x75C
#define NV_PERF_PMASYS_ENGINESTATUS_STATUS_SHIFT 0
#define NV_PERF_PMASYS_ENGINESTATUS_STATUS_MASK 0x00000007
#define NV_PERF_PMASYS_ENGINESTATUS_STATUS_EMPTY 0x00000000
#define NV_PERF_PMASYS_ENGINESTATUS_STATUS_ACTIVE 0x00000001
#define NV_PERF_PMASYS_ENGINESTATUS_STATUS_PAUSED 0x00000002
#define NV_PERF_PMASYS_ENGINESTATUS_STATUS_QUIESCENT 0x00000003
#define NV_PERF_PMASYS_ENGINESTATUS_STATUS_STALLED 0x00000005
#define NV_PERF_PMASYS_ENGINESTATUS_STATUS_FAULTED 0x00000006
#define NV_PERF_PMASYS_ENGINESTATUS_STATUS_HALTED 0x00000007
#define NV_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY_SHIFT 4
#define NV_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY_MASK 0x00000010
#define NV_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY_EMPTY 0x00000001
#define NV_PERF_PMASYS_ENGINESTATUS_MBU_STATUS_SHIFT 5
#define NV_PERF_PMASYS_ENGINESTATUS_MBU_STATUS_MASK 0x00000060
#define NV_PERF_PMASYS_ENGINESTATUS_MBU_STATUS_IDLE 0x00000000
#define NV_PERF_PMASYS_ENGINESTATUS_MBU_STATUS_BUSY 0x00000001
#define NV_PERF_PMASYS_ENGINESTATUS_MBU_STATUS_PENDING 0x00000002
/* RTR Aperture */
#define NV_ADDRESS_MAP_RTR_BASE 0x0f14d000
#define NV_ADDRESS_MAP_RTR_LIMIT 0x0f14dfff
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS 0x10
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_SHIFT 0
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_MASK 0x00000007
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_EMPTY 0x00000000
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_ACTIVE 0x00000001
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_PAUSED 0x00000002
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_QUIESCENT 0x00000003
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_STALLED 0x00000005
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_FAULTED 0x00000006
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_HALTED 0x00000007
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_ENABLE_SHIFT 8
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_ENABLE_MASK 0x00000100
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_ENABLE_MASKED 0x0
#define NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_ENABLE_OUT 0x1
#define NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS 0x14
#define NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED_SHIFT 0
#define NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED_MASK 0x00000007
#define NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED_EMPTY 0x00000000
#define NV_PERF_PMMSYS_SYS0ROUTER_CG2 0x18
#define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_SHIFT 0
#define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_MASK 0x3
#define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_ENABLED 0x00000000
#define NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_DISABLED 0x00000003
/* Display Aperture */
#define NV_ADDRESS_MAP_DISP_BASE 0x13800000
#define NV_ADDRESS_MAP_DISP_LIMIT 0x138effff
/* VI Apertures */
#define NV_ADDRESS_MAP_VI_THI_BASE 0x15f00000
#define NV_ADDRESS_MAP_VI_THI_LIMIT 0x15ffffff
#define NV_ADDRESS_MAP_VI2_THI_BASE 0x14f00000
#define NV_ADDRESS_MAP_VI2_THI_LIMIT 0x14ffffff
/* VIC Aperture */
#define NV_ADDRESS_MAP_VIC_BASE 0x15340000
#define NV_ADDRESS_MAP_VIC_LIMIT 0x1537ffff
/* NVDEC Aperture */
#define NV_ADDRESS_MAP_NVDEC_BASE 0x15480000
#define NV_ADDRESS_MAP_NVDEC_LIMIT 0x154bffff
/* NVENC Aperture */
#define NV_ADDRESS_MAP_NVENC_BASE 0x154c0000
#define NV_ADDRESS_MAP_NVENC_LIMIT 0x154fffff
/* OFA Aperture */
#define NV_ADDRESS_MAP_OFA_BASE 0x15a50000
#define NV_ADDRESS_MAP_OFA_LIMIT 0x15a5ffff
/* ISP Aperture */
#define NV_ADDRESS_MAP_ISP_THI_BASE 0x14b00000
#define NV_ADDRESS_MAP_ISP_THI_LIMIT 0x14bfffff
/* PCIE Apertures */
#define NV_ADDRESS_MAP_PCIE_C0_CTL_BASE 0x14180000
#define NV_ADDRESS_MAP_PCIE_C0_CTL_LIMIT 0x1419ffff
#define NV_ADDRESS_MAP_PCIE_C1_CTL_BASE 0x14100000
#define NV_ADDRESS_MAP_PCIE_C1_CTL_LIMIT 0x1411ffff
#define NV_ADDRESS_MAP_PCIE_C2_CTL_BASE 0x14120000
#define NV_ADDRESS_MAP_PCIE_C2_CTL_LIMIT 0x1413ffff
#define NV_ADDRESS_MAP_PCIE_C3_CTL_BASE 0x14140000
#define NV_ADDRESS_MAP_PCIE_C3_CTL_LIMIT 0x1415ffff
#define NV_ADDRESS_MAP_PCIE_C4_CTL_BASE 0x14160000
#define NV_ADDRESS_MAP_PCIE_C4_CTL_LIMIT 0x1417ffff
#define NV_ADDRESS_MAP_PCIE_C5_CTL_BASE 0x141a0000
#define NV_ADDRESS_MAP_PCIE_C5_CTL_LIMIT 0x141bffff
#define NV_ADDRESS_MAP_PCIE_C6_CTL_BASE 0x141c0000
#define NV_ADDRESS_MAP_PCIE_C6_CTL_LIMIT 0x141dffff
#define NV_ADDRESS_MAP_PCIE_C7_CTL_BASE 0x141e0000
#define NV_ADDRESS_MAP_PCIE_C7_CTL_LIMIT 0x141fffff
#define NV_ADDRESS_MAP_PCIE_C8_CTL_BASE 0x140a0000
#define NV_ADDRESS_MAP_PCIE_C8_CTL_LIMIT 0x140bffff
#define NV_ADDRESS_MAP_PCIE_C9_CTL_BASE 0x140c0000
#define NV_ADDRESS_MAP_PCIE_C9_CTL_LIMIT 0x140dffff
#define NV_ADDRESS_MAP_PCIE_C10_CTL_BASE 0x140e0000
#define NV_ADDRESS_MAP_PCIE_C10_CTL_LIMIT 0x140fffff
/* PVA Aperture */
#define NV_ADDRESS_MAP_PVA0_PM_BASE 0x16200000
#define NV_ADDRESS_MAP_PVA0_PM_LIMIT 0x1620ffff
/* NVDLA Apertures */
#define NV_ADDRESS_MAP_NVDLA0_BASE 0x15880000
#define NV_ADDRESS_MAP_NVDLA0_LIMIT 0x158bffff
#define NV_ADDRESS_MAP_NVDLA1_BASE 0x158c0000
#define NV_ADDRESS_MAP_NVDLA1_LIMIT 0x158fffff
/* MGBE Apertures */
#define NV_ADDRESS_MAP_MGBE0_BASE 0x06800000
#define NV_ADDRESS_MAP_MGBE0_LIMIT 0x068fffff
#define NV_ADDRESS_MAP_MGBE1_BASE 0x06900000
#define NV_ADDRESS_MAP_MGBE1_LIMIT 0x069fffff
#define NV_ADDRESS_MAP_MGBE2_BASE 0x06a00000
#define NV_ADDRESS_MAP_MGBE2_LIMIT 0x06afffff
#define NV_ADDRESS_MAP_MGBE3_BASE 0x06b00000
#define NV_ADDRESS_MAP_MGBE3_LIMIT 0x06bfffff
/* MC Apertures */
#define NV_ADDRESS_MAP_MCB_BASE 0x02c10000
#define NV_ADDRESS_MAP_MCB_LIMIT 0x02c1ffff
#define NV_ADDRESS_MAP_MC0_BASE 0x02c20000
#define NV_ADDRESS_MAP_MC0_LIMIT 0x02c2ffff
#define NV_ADDRESS_MAP_MC1_BASE 0x02c30000
#define NV_ADDRESS_MAP_MC1_LIMIT 0x02c3ffff
#define NV_ADDRESS_MAP_MC2_BASE 0x02c40000
#define NV_ADDRESS_MAP_MC2_LIMIT 0x02c4ffff
#define NV_ADDRESS_MAP_MC3_BASE 0x02c50000
#define NV_ADDRESS_MAP_MC3_LIMIT 0x02c5ffff
#define NV_ADDRESS_MAP_MC4_BASE 0x02b80000
#define NV_ADDRESS_MAP_MC4_LIMIT 0x02b8ffff
#define NV_ADDRESS_MAP_MC5_BASE 0x02b90000
#define NV_ADDRESS_MAP_MC5_LIMIT 0x02b9ffff
#define NV_ADDRESS_MAP_MC6_BASE 0x02ba0000
#define NV_ADDRESS_MAP_MC6_LIMIT 0x02baffff
#define NV_ADDRESS_MAP_MC7_BASE 0x02bb0000
#define NV_ADDRESS_MAP_MC7_LIMIT 0x02bbffff
#define NV_ADDRESS_MAP_MC8_BASE 0x01700000
#define NV_ADDRESS_MAP_MC8_LIMIT 0x0170ffff
#define NV_ADDRESS_MAP_MC9_BASE 0x01710000
#define NV_ADDRESS_MAP_MC9_LIMIT 0x0171ffff
#define NV_ADDRESS_MAP_MC10_BASE 0x01720000
#define NV_ADDRESS_MAP_MC10_LIMIT 0x0172ffff
#define NV_ADDRESS_MAP_MC11_BASE 0x01730000
#define NV_ADDRESS_MAP_MC11_LIMIT 0x0173ffff
#define NV_ADDRESS_MAP_MC12_BASE 0x01740000
#define NV_ADDRESS_MAP_MC12_LIMIT 0x0174ffff
#define NV_ADDRESS_MAP_MC13_BASE 0x01750000
#define NV_ADDRESS_MAP_MC13_LIMIT 0x0175ffff
#define NV_ADDRESS_MAP_MC14_BASE 0x01760000
#define NV_ADDRESS_MAP_MC14_LIMIT 0x0176ffff
#define NV_ADDRESS_MAP_MC15_BASE 0x01770000
#define NV_ADDRESS_MAP_MC15_LIMIT 0x0177ffff
/* MSSNVLINK Apertures */
#define NV_ADDRESS_MAP_MSS_NVLINK_1_BASE 0x01f20000
#define NV_ADDRESS_MAP_MSS_NVLINK_1_LIMIT 0x01f3ffff
#define NV_ADDRESS_MAP_MSS_NVLINK_2_BASE 0x01f40000
#define NV_ADDRESS_MAP_MSS_NVLINK_2_LIMIT 0x01f5ffff
#define NV_ADDRESS_MAP_MSS_NVLINK_3_BASE 0x01f60000
#define NV_ADDRESS_MAP_MSS_NVLINK_3_LIMIT 0x01f7ffff
#define NV_ADDRESS_MAP_MSS_NVLINK_4_BASE 0x01f80000
#define NV_ADDRESS_MAP_MSS_NVLINK_4_LIMIT 0x01f9ffff
#define NV_ADDRESS_MAP_MSS_NVLINK_5_BASE 0x01fa0000
#define NV_ADDRESS_MAP_MSS_NVLINK_5_LIMIT 0x01fbffff
#define NV_ADDRESS_MAP_MSS_NVLINK_6_BASE 0x01fc0000
#define NV_ADDRESS_MAP_MSS_NVLINK_6_LIMIT 0x01fdffff
#define NV_ADDRESS_MAP_MSS_NVLINK_7_BASE 0x01fe0000
#define NV_ADDRESS_MAP_MSS_NVLINK_7_LIMIT 0x01ffffff
#define NV_ADDRESS_MAP_MSS_NVLINK_8_BASE 0x01e00000
#define NV_ADDRESS_MAP_MSS_NVLINK_8_LIMIT 0x01e1ffff
#define PERFMON_BASE(ip_idx) (addr_map_rpg_pm_base_r() + \
((u32)(ip_idx)) * pmmsys_perdomain_offset_v())
#define PERFMON_LIMIT(ip_idx) (PERFMON_BASE((ip_idx) + 1) - 1)
#endif /* TEGRA_SOC_HWPM_HW_H */

319
tegra-soc-hwpm-io.c
View File

@@ -19,6 +19,7 @@
*/
#include "tegra-soc-hwpm-io.h"
#include "include/hw/t234/hw_addr_map_soc_hwpm.h"
/* FIXME: Auto-generate whitelists */
struct whitelist perfmon_wlist[] = {
@@ -139,8 +140,8 @@ struct hwpm_resource_aperture vi_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_VI1_PERFMON_DT,
},
{
.start_pa = NV_ADDRESS_MAP_VI_THI_BASE,
.end_pa = NV_ADDRESS_MAP_VI_THI_LIMIT,
.start_pa = addr_map_vi_thi_base_r(),
.end_pa = addr_map_vi_thi_limit_r(),
.fake_registers = NULL,
.wlist = vi_thi_wlist,
.wlist_size = ARRAY_SIZE(vi_thi_wlist),
@@ -148,8 +149,8 @@ struct hwpm_resource_aperture vi_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_VI2_THI_BASE,
.end_pa = NV_ADDRESS_MAP_VI2_THI_LIMIT,
.start_pa = addr_map_vi2_thi_base_r(),
.end_pa = addr_map_vi2_thi_limit_r(),
.fake_registers = NULL,
.wlist = vi2_thi_wlist,
.wlist_size = ARRAY_SIZE(vi2_thi_wlist),
@@ -179,8 +180,8 @@ struct hwpm_resource_aperture isp_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_ISP0_PERFMON_DT,
},
{
.start_pa = NV_ADDRESS_MAP_ISP_THI_BASE,
.end_pa = NV_ADDRESS_MAP_ISP_THI_LIMIT,
.start_pa = addr_map_isp_thi_base_r(),
.end_pa = addr_map_isp_thi_limit_r(),
.fake_registers = NULL,
.wlist = isp_thi_wlist,
.wlist_size = ARRAY_SIZE(isp_thi_wlist),
@@ -211,8 +212,8 @@ struct hwpm_resource_aperture vic_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_VICA0_PERFMON_DT,
},
{
.start_pa = NV_ADDRESS_MAP_VIC_BASE,
.end_pa = NV_ADDRESS_MAP_VIC_LIMIT,
.start_pa = addr_map_vic_base_r(),
.end_pa = addr_map_vic_limit_r(),
.fake_registers = NULL,
.wlist = vic_wlist,
.wlist_size = ARRAY_SIZE(vic_wlist),
@@ -241,8 +242,8 @@ struct hwpm_resource_aperture ofa_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_OFAA0_PERFMON_DT,
},
{
.start_pa = NV_ADDRESS_MAP_OFA_BASE,
.end_pa = NV_ADDRESS_MAP_OFA_LIMIT,
.start_pa = addr_map_ofa_base_r(),
.end_pa = addr_map_ofa_limit_r(),
.fake_registers = NULL,
.wlist = ofa_wlist,
.wlist_size = ARRAY_SIZE(ofa_wlist),
@@ -292,8 +293,8 @@ struct hwpm_resource_aperture pva_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_PVAC0_PERFMON_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PVA0_PM_BASE,
.end_pa = NV_ADDRESS_MAP_PVA0_PM_LIMIT,
.start_pa = addr_map_pva0_pm_base_r(),
.end_pa = addr_map_pva0_pm_limit_r(),
.fake_registers = NULL,
.wlist = pva0_pm_wlist,
.wlist_size = ARRAY_SIZE(pva0_pm_wlist),
@@ -333,8 +334,8 @@ struct hwpm_resource_aperture nvdla_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_NVDLAB1_PERFMON_DT,
},
{
.start_pa = NV_ADDRESS_MAP_NVDLA0_BASE,
.end_pa = NV_ADDRESS_MAP_NVDLA0_LIMIT,
.start_pa = addr_map_nvdla0_base_r(),
.end_pa = addr_map_nvdla0_limit_r(),
.fake_registers = NULL,
.wlist = nvdla_wlist,
.wlist_size = ARRAY_SIZE(nvdla_wlist),
@@ -342,8 +343,8 @@ struct hwpm_resource_aperture nvdla_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_NVDLA1_BASE,
.end_pa = NV_ADDRESS_MAP_NVDLA1_LIMIT,
.start_pa = addr_map_nvdla1_base_r(),
.end_pa = addr_map_nvdla1_limit_r(),
.fake_registers = NULL,
.wlist = nvdla_wlist,
.wlist_size = ARRAY_SIZE(nvdla_wlist),
@@ -394,8 +395,8 @@ struct hwpm_resource_aperture mgbe_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_MGBE3_PERFMON_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MGBE0_BASE,
.end_pa = NV_ADDRESS_MAP_MGBE0_LIMIT,
.start_pa = addr_map_mgbe0_base_r(),
.end_pa = addr_map_mgbe0_limit_r(),
.fake_registers = NULL,
.wlist = mgbe_wlist,
.wlist_size = ARRAY_SIZE(mgbe_wlist),
@@ -403,8 +404,8 @@ struct hwpm_resource_aperture mgbe_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MGBE1_BASE,
.end_pa = NV_ADDRESS_MAP_MGBE1_LIMIT,
.start_pa = addr_map_mgbe1_base_r(),
.end_pa = addr_map_mgbe1_limit_r(),
.fake_registers = NULL,
.wlist = mgbe_wlist,
.wlist_size = ARRAY_SIZE(mgbe_wlist),
@@ -412,8 +413,8 @@ struct hwpm_resource_aperture mgbe_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MGBE2_BASE,
.end_pa = NV_ADDRESS_MAP_MGBE2_LIMIT,
.start_pa = addr_map_mgbe2_base_r(),
.end_pa = addr_map_mgbe2_limit_r(),
.fake_registers = NULL,
.wlist = mgbe_wlist,
.wlist_size = ARRAY_SIZE(mgbe_wlist),
@@ -421,8 +422,8 @@ struct hwpm_resource_aperture mgbe_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MGBE3_BASE,
.end_pa = NV_ADDRESS_MAP_MGBE3_LIMIT,
.start_pa = addr_map_mgbe3_base_r(),
.end_pa = addr_map_mgbe3_limit_r(),
.fake_registers = NULL,
.wlist = mgbe_wlist,
.wlist_size = ARRAY_SIZE(mgbe_wlist),
@@ -463,8 +464,8 @@ struct hwpm_resource_aperture nvdec_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_NVDECA0_PERFMON_DT,
},
{
.start_pa = NV_ADDRESS_MAP_NVDEC_BASE,
.end_pa = NV_ADDRESS_MAP_NVDEC_LIMIT,
.start_pa = addr_map_nvdec_base_r(),
.end_pa = addr_map_nvdec_limit_r(),
.fake_registers = NULL,
.wlist = nvdec_wlist,
.wlist_size = ARRAY_SIZE(nvdec_wlist),
@@ -490,8 +491,8 @@ struct hwpm_resource_aperture nvenc_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_NVENCA0_PERFMON_DT,
},
{
.start_pa = NV_ADDRESS_MAP_NVENC_BASE,
.end_pa = NV_ADDRESS_MAP_NVENC_LIMIT,
.start_pa = addr_map_nvenc_base_r(),
.end_pa = addr_map_nvenc_limit_r(),
.fake_registers = NULL,
.wlist = nvenc_wlist,
.wlist_size = ARRAY_SIZE(nvenc_wlist),
@@ -605,8 +606,8 @@ struct hwpm_resource_aperture pcie_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_PCIE10_PERFMON_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PCIE_C0_CTL_BASE,
.end_pa = NV_ADDRESS_MAP_PCIE_C0_CTL_LIMIT,
.start_pa = addr_map_pcie_c0_ctl_base_r(),
.end_pa = addr_map_pcie_c0_ctl_limit_r(),
.fake_registers = NULL,
.wlist = pcie_ctl_wlist,
.wlist_size = ARRAY_SIZE(pcie_ctl_wlist),
@@ -614,8 +615,8 @@ struct hwpm_resource_aperture pcie_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PCIE_C1_CTL_BASE,
.end_pa = NV_ADDRESS_MAP_PCIE_C1_CTL_LIMIT,
.start_pa = addr_map_pcie_c1_ctl_base_r(),
.end_pa = addr_map_pcie_c1_ctl_limit_r(),
.fake_registers = NULL,
.wlist = pcie_ctl_wlist,
.wlist_size = ARRAY_SIZE(pcie_ctl_wlist),
@@ -623,8 +624,8 @@ struct hwpm_resource_aperture pcie_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PCIE_C2_CTL_BASE,
.end_pa = NV_ADDRESS_MAP_PCIE_C2_CTL_LIMIT,
.start_pa = addr_map_pcie_c2_ctl_base_r(),
.end_pa = addr_map_pcie_c2_ctl_limit_r(),
.fake_registers = NULL,
.wlist = pcie_ctl_wlist,
.wlist_size = ARRAY_SIZE(pcie_ctl_wlist),
@@ -632,8 +633,8 @@ struct hwpm_resource_aperture pcie_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PCIE_C3_CTL_BASE,
.end_pa = NV_ADDRESS_MAP_PCIE_C3_CTL_LIMIT,
.start_pa = addr_map_pcie_c3_ctl_base_r(),
.end_pa = addr_map_pcie_c3_ctl_limit_r(),
.fake_registers = NULL,
.wlist = pcie_ctl_wlist,
.wlist_size = ARRAY_SIZE(pcie_ctl_wlist),
@@ -641,8 +642,8 @@ struct hwpm_resource_aperture pcie_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PCIE_C4_CTL_BASE,
.end_pa = NV_ADDRESS_MAP_PCIE_C4_CTL_LIMIT,
.start_pa = addr_map_pcie_c4_ctl_base_r(),
.end_pa = addr_map_pcie_c4_ctl_limit_r(),
.fake_registers = NULL,
.wlist = pcie_ctl_wlist,
.wlist_size = ARRAY_SIZE(pcie_ctl_wlist),
@@ -650,8 +651,8 @@ struct hwpm_resource_aperture pcie_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PCIE_C5_CTL_BASE,
.end_pa = NV_ADDRESS_MAP_PCIE_C5_CTL_LIMIT,
.start_pa = addr_map_pcie_c5_ctl_base_r(),
.end_pa = addr_map_pcie_c5_ctl_limit_r(),
.fake_registers = NULL,
.wlist = pcie_ctl_wlist,
.wlist_size = ARRAY_SIZE(pcie_ctl_wlist),
@@ -659,8 +660,8 @@ struct hwpm_resource_aperture pcie_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PCIE_C6_CTL_BASE,
.end_pa = NV_ADDRESS_MAP_PCIE_C6_CTL_LIMIT,
.start_pa = addr_map_pcie_c6_ctl_base_r(),
.end_pa = addr_map_pcie_c6_ctl_limit_r(),
.fake_registers = NULL,
.wlist = pcie_ctl_wlist,
.wlist_size = ARRAY_SIZE(pcie_ctl_wlist),
@@ -668,8 +669,8 @@ struct hwpm_resource_aperture pcie_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PCIE_C7_CTL_BASE,
.end_pa = NV_ADDRESS_MAP_PCIE_C7_CTL_LIMIT,
.start_pa = addr_map_pcie_c7_ctl_base_r(),
.end_pa = addr_map_pcie_c7_ctl_limit_r(),
.fake_registers = NULL,
.wlist = pcie_ctl_wlist,
.wlist_size = ARRAY_SIZE(pcie_ctl_wlist),
@@ -677,8 +678,8 @@ struct hwpm_resource_aperture pcie_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PCIE_C8_CTL_BASE,
.end_pa = NV_ADDRESS_MAP_PCIE_C8_CTL_LIMIT,
.start_pa = addr_map_pcie_c8_ctl_base_r(),
.end_pa = addr_map_pcie_c8_ctl_limit_r(),
.fake_registers = NULL,
.wlist = pcie_ctl_wlist,
.wlist_size = ARRAY_SIZE(pcie_ctl_wlist),
@@ -686,8 +687,8 @@ struct hwpm_resource_aperture pcie_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PCIE_C9_CTL_BASE,
.end_pa = NV_ADDRESS_MAP_PCIE_C9_CTL_LIMIT,
.start_pa = addr_map_pcie_c9_ctl_base_r(),
.end_pa = addr_map_pcie_c9_ctl_limit_r(),
.fake_registers = NULL,
.wlist = pcie_ctl_wlist,
.wlist_size = ARRAY_SIZE(pcie_ctl_wlist),
@@ -695,8 +696,8 @@ struct hwpm_resource_aperture pcie_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_PCIE_C10_CTL_BASE,
.end_pa = NV_ADDRESS_MAP_PCIE_C10_CTL_LIMIT,
.start_pa = addr_map_pcie_c10_ctl_base_r(),
.end_pa = addr_map_pcie_c10_ctl_limit_r(),
.fake_registers = NULL,
.wlist = pcie_ctl_wlist,
.wlist_size = ARRAY_SIZE(pcie_ctl_wlist),
@@ -721,8 +722,8 @@ struct hwpm_resource_aperture display_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_NVDISPLAY0_PERFMON_DT,
},
{
.start_pa = NV_ADDRESS_MAP_DISP_BASE,
.end_pa = NV_ADDRESS_MAP_DISP_LIMIT,
.start_pa = addr_map_disp_base_r(),
.end_pa = addr_map_disp_limit_r(),
.fake_registers = NULL,
.wlist = disp_wlist,
.wlist_size = ARRAY_SIZE(disp_wlist),
@@ -747,8 +748,8 @@ struct whitelist mc_res_mss_channel_wlist[] = {
};
struct hwpm_resource_aperture mss_channel_map[] = {
{
.start_pa = NV_ADDRESS_MAP_MC0_BASE,
.end_pa = NV_ADDRESS_MAP_MC0_LIMIT,
.start_pa = addr_map_mc0_base_r(),
.end_pa = addr_map_mc0_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -756,8 +757,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC1_BASE,
.end_pa = NV_ADDRESS_MAP_MC1_LIMIT,
.start_pa = addr_map_mc1_base_r(),
.end_pa = addr_map_mc1_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -765,8 +766,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC2_BASE,
.end_pa = NV_ADDRESS_MAP_MC2_LIMIT,
.start_pa = addr_map_mc2_base_r(),
.end_pa = addr_map_mc2_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -774,8 +775,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC3_BASE,
.end_pa = NV_ADDRESS_MAP_MC3_LIMIT,
.start_pa = addr_map_mc3_base_r(),
.end_pa = addr_map_mc3_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -783,8 +784,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC4_BASE,
.end_pa = NV_ADDRESS_MAP_MC4_LIMIT,
.start_pa = addr_map_mc4_base_r(),
.end_pa = addr_map_mc4_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -792,8 +793,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC5_BASE,
.end_pa = NV_ADDRESS_MAP_MC5_LIMIT,
.start_pa = addr_map_mc5_base_r(),
.end_pa = addr_map_mc5_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -801,8 +802,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC6_BASE,
.end_pa = NV_ADDRESS_MAP_MC6_LIMIT,
.start_pa = addr_map_mc6_base_r(),
.end_pa = addr_map_mc6_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -810,8 +811,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC7_BASE,
.end_pa = NV_ADDRESS_MAP_MC7_LIMIT,
.start_pa = addr_map_mc7_base_r(),
.end_pa = addr_map_mc7_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -819,8 +820,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC8_BASE,
.end_pa = NV_ADDRESS_MAP_MC8_LIMIT,
.start_pa = addr_map_mc8_base_r(),
.end_pa = addr_map_mc8_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -828,8 +829,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC9_BASE,
.end_pa = NV_ADDRESS_MAP_MC9_LIMIT,
.start_pa = addr_map_mc9_base_r(),
.end_pa = addr_map_mc9_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -837,8 +838,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC10_BASE,
.end_pa = NV_ADDRESS_MAP_MC10_LIMIT,
.start_pa = addr_map_mc10_base_r(),
.end_pa = addr_map_mc10_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -846,8 +847,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC11_BASE,
.end_pa = NV_ADDRESS_MAP_MC11_LIMIT,
.start_pa = addr_map_mc11_base_r(),
.end_pa = addr_map_mc11_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -855,8 +856,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC12_BASE,
.end_pa = NV_ADDRESS_MAP_MC12_LIMIT,
.start_pa = addr_map_mc12_base_r(),
.end_pa = addr_map_mc12_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -864,8 +865,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC13_BASE,
.end_pa = NV_ADDRESS_MAP_MC13_LIMIT,
.start_pa = addr_map_mc13_base_r(),
.end_pa = addr_map_mc13_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -873,8 +874,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC14_BASE,
.end_pa = NV_ADDRESS_MAP_MC14_LIMIT,
.start_pa = addr_map_mc14_base_r(),
.end_pa = addr_map_mc14_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -882,8 +883,8 @@ struct hwpm_resource_aperture mss_channel_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC15_BASE,
.end_pa = NV_ADDRESS_MAP_MC15_LIMIT,
.start_pa = addr_map_mc15_base_r(),
.end_pa = addr_map_mc15_limit_r(),
.fake_registers = NULL,
.wlist = mc_res_mss_channel_wlist,
.wlist_size = ARRAY_SIZE(mc_res_mss_channel_wlist),
@@ -1042,8 +1043,8 @@ struct whitelist mss_nvlink_wlist[] = {
};
struct hwpm_resource_aperture mss_gpu_hub_map[] = {
{
.start_pa = NV_ADDRESS_MAP_MSS_NVLINK_1_BASE,
.end_pa = NV_ADDRESS_MAP_MSS_NVLINK_1_LIMIT,
.start_pa = addr_map_mss_nvlink_1_base_r(),
.end_pa = addr_map_mss_nvlink_1_limit_r(),
.fake_registers = NULL,
.wlist = mss_nvlink_wlist,
.wlist_size = ARRAY_SIZE(mss_nvlink_wlist),
@@ -1051,8 +1052,8 @@ struct hwpm_resource_aperture mss_gpu_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MSS_NVLINK_2_BASE,
.end_pa = NV_ADDRESS_MAP_MSS_NVLINK_2_LIMIT,
.start_pa = addr_map_mss_nvlink_2_base_r(),
.end_pa = addr_map_mss_nvlink_2_limit_r(),
.fake_registers = NULL,
.wlist = mss_nvlink_wlist,
.wlist_size = ARRAY_SIZE(mss_nvlink_wlist),
@@ -1060,8 +1061,8 @@ struct hwpm_resource_aperture mss_gpu_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MSS_NVLINK_3_BASE,
.end_pa = NV_ADDRESS_MAP_MSS_NVLINK_3_LIMIT,
.start_pa = addr_map_mss_nvlink_3_base_r(),
.end_pa = addr_map_mss_nvlink_3_limit_r(),
.fake_registers = NULL,
.wlist = mss_nvlink_wlist,
.wlist_size = ARRAY_SIZE(mss_nvlink_wlist),
@@ -1069,8 +1070,8 @@ struct hwpm_resource_aperture mss_gpu_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MSS_NVLINK_4_BASE,
.end_pa = NV_ADDRESS_MAP_MSS_NVLINK_4_LIMIT,
.start_pa = addr_map_mss_nvlink_4_base_r(),
.end_pa = addr_map_mss_nvlink_4_limit_r(),
.fake_registers = NULL,
.wlist = mss_nvlink_wlist,
.wlist_size = ARRAY_SIZE(mss_nvlink_wlist),
@@ -1078,8 +1079,8 @@ struct hwpm_resource_aperture mss_gpu_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MSS_NVLINK_5_BASE,
.end_pa = NV_ADDRESS_MAP_MSS_NVLINK_5_LIMIT,
.start_pa = addr_map_mss_nvlink_5_base_r(),
.end_pa = addr_map_mss_nvlink_5_limit_r(),
.fake_registers = NULL,
.wlist = mss_nvlink_wlist,
.wlist_size = ARRAY_SIZE(mss_nvlink_wlist),
@@ -1087,8 +1088,8 @@ struct hwpm_resource_aperture mss_gpu_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MSS_NVLINK_6_BASE,
.end_pa = NV_ADDRESS_MAP_MSS_NVLINK_6_LIMIT,
.start_pa = addr_map_mss_nvlink_6_base_r(),
.end_pa = addr_map_mss_nvlink_6_limit_r(),
.fake_registers = NULL,
.wlist = mss_nvlink_wlist,
.wlist_size = ARRAY_SIZE(mss_nvlink_wlist),
@@ -1096,8 +1097,8 @@ struct hwpm_resource_aperture mss_gpu_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MSS_NVLINK_7_BASE,
.end_pa = NV_ADDRESS_MAP_MSS_NVLINK_7_LIMIT,
.start_pa = addr_map_mss_nvlink_7_base_r(),
.end_pa = addr_map_mss_nvlink_7_limit_r(),
.fake_registers = NULL,
.wlist = mss_nvlink_wlist,
.wlist_size = ARRAY_SIZE(mss_nvlink_wlist),
@@ -1105,8 +1106,8 @@ struct hwpm_resource_aperture mss_gpu_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MSS_NVLINK_8_BASE,
.end_pa = NV_ADDRESS_MAP_MSS_NVLINK_8_LIMIT,
.start_pa = addr_map_mss_nvlink_8_base_r(),
.end_pa = addr_map_mss_nvlink_8_limit_r(),
.fake_registers = NULL,
.wlist = mss_nvlink_wlist,
.wlist_size = ARRAY_SIZE(mss_nvlink_wlist),
@@ -1135,8 +1136,8 @@ struct whitelist mc8_res_mss_iso_niso_hub_wlist[] = {
};
struct hwpm_resource_aperture mss_iso_niso_hub_map[] = {
{
.start_pa = NV_ADDRESS_MAP_MC0_BASE,
.end_pa = NV_ADDRESS_MAP_MC0_LIMIT,
.start_pa = addr_map_mc0_base_r(),
.end_pa = addr_map_mc0_limit_r(),
.fake_registers = NULL,
.wlist = mc0to7_res_mss_iso_niso_hub_wlist,
.wlist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_wlist),
@@ -1144,8 +1145,8 @@ struct hwpm_resource_aperture mss_iso_niso_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC1_BASE,
.end_pa = NV_ADDRESS_MAP_MC1_LIMIT,
.start_pa = addr_map_mc1_base_r(),
.end_pa = addr_map_mc1_limit_r(),
.fake_registers = NULL,
.wlist = mc0to7_res_mss_iso_niso_hub_wlist,
.wlist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_wlist),
@@ -1153,8 +1154,8 @@ struct hwpm_resource_aperture mss_iso_niso_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC2_BASE,
.end_pa = NV_ADDRESS_MAP_MC2_LIMIT,
.start_pa = addr_map_mc2_base_r(),
.end_pa = addr_map_mc2_limit_r(),
.fake_registers = NULL,
.wlist = mc0to7_res_mss_iso_niso_hub_wlist,
.wlist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_wlist),
@@ -1162,8 +1163,8 @@ struct hwpm_resource_aperture mss_iso_niso_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC3_BASE,
.end_pa = NV_ADDRESS_MAP_MC3_LIMIT,
.start_pa = addr_map_mc3_base_r(),
.end_pa = addr_map_mc3_limit_r(),
.fake_registers = NULL,
.wlist = mc0to7_res_mss_iso_niso_hub_wlist,
.wlist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_wlist),
@@ -1171,8 +1172,8 @@ struct hwpm_resource_aperture mss_iso_niso_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC4_BASE,
.end_pa = NV_ADDRESS_MAP_MC4_LIMIT,
.start_pa = addr_map_mc4_base_r(),
.end_pa = addr_map_mc4_limit_r(),
.fake_registers = NULL,
.wlist = mc0to7_res_mss_iso_niso_hub_wlist,
.wlist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_wlist),
@@ -1180,8 +1181,8 @@ struct hwpm_resource_aperture mss_iso_niso_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC5_BASE,
.end_pa = NV_ADDRESS_MAP_MC5_LIMIT,
.start_pa = addr_map_mc5_base_r(),
.end_pa = addr_map_mc5_limit_r(),
.fake_registers = NULL,
.wlist = mc0to7_res_mss_iso_niso_hub_wlist,
.wlist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_wlist),
@@ -1189,8 +1190,8 @@ struct hwpm_resource_aperture mss_iso_niso_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC6_BASE,
.end_pa = NV_ADDRESS_MAP_MC6_LIMIT,
.start_pa = addr_map_mc6_base_r(),
.end_pa = addr_map_mc6_limit_r(),
.fake_registers = NULL,
.wlist = mc0to7_res_mss_iso_niso_hub_wlist,
.wlist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_wlist),
@@ -1198,8 +1199,8 @@ struct hwpm_resource_aperture mss_iso_niso_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC7_BASE,
.end_pa = NV_ADDRESS_MAP_MC7_LIMIT,
.start_pa = addr_map_mc7_base_r(),
.end_pa = addr_map_mc7_limit_r(),
.fake_registers = NULL,
.wlist = mc0to7_res_mss_iso_niso_hub_wlist,
.wlist_size = ARRAY_SIZE(mc0to7_res_mss_iso_niso_hub_wlist),
@@ -1207,8 +1208,8 @@ struct hwpm_resource_aperture mss_iso_niso_hub_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC8_BASE,
.end_pa = NV_ADDRESS_MAP_MC8_LIMIT,
.start_pa = addr_map_mc8_base_r(),
.end_pa = addr_map_mc8_limit_r(),
.fake_registers = NULL,
.wlist = mc8_res_mss_iso_niso_hub_wlist,
.wlist_size = ARRAY_SIZE(mc8_res_mss_iso_niso_hub_wlist),
@@ -1254,8 +1255,8 @@ struct whitelist mc2to7_res_mss_mcf_wlist[] = {
};
struct hwpm_resource_aperture mss_mcf_map[] = {
{
.start_pa = NV_ADDRESS_MAP_MC0_BASE,
.end_pa = NV_ADDRESS_MAP_MC0_LIMIT,
.start_pa = addr_map_mc0_base_r(),
.end_pa = addr_map_mc0_limit_r(),
.fake_registers = NULL,
.wlist = mc0to1_res_mss_mcf_wlist,
.wlist_size = ARRAY_SIZE(mc0to1_res_mss_mcf_wlist),
@@ -1263,8 +1264,8 @@ struct hwpm_resource_aperture mss_mcf_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC1_BASE,
.end_pa = NV_ADDRESS_MAP_MC1_LIMIT,
.start_pa = addr_map_mc1_base_r(),
.end_pa = addr_map_mc1_limit_r(),
.fake_registers = NULL,
.wlist = mc0to1_res_mss_mcf_wlist,
.wlist_size = ARRAY_SIZE(mc0to1_res_mss_mcf_wlist),
@@ -1272,8 +1273,8 @@ struct hwpm_resource_aperture mss_mcf_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC2_BASE,
.end_pa = NV_ADDRESS_MAP_MC2_LIMIT,
.start_pa = addr_map_mc2_base_r(),
.end_pa = addr_map_mc2_limit_r(),
.fake_registers = NULL,
.wlist = mc2to7_res_mss_mcf_wlist,
.wlist_size = ARRAY_SIZE(mc2to7_res_mss_mcf_wlist),
@@ -1281,8 +1282,8 @@ struct hwpm_resource_aperture mss_mcf_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC3_BASE,
.end_pa = NV_ADDRESS_MAP_MC3_LIMIT,
.start_pa = addr_map_mc3_base_r(),
.end_pa = addr_map_mc3_limit_r(),
.fake_registers = NULL,
.wlist = mc2to7_res_mss_mcf_wlist,
.wlist_size = ARRAY_SIZE(mc2to7_res_mss_mcf_wlist),
@@ -1290,8 +1291,8 @@ struct hwpm_resource_aperture mss_mcf_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC4_BASE,
.end_pa = NV_ADDRESS_MAP_MC4_LIMIT,
.start_pa = addr_map_mc4_base_r(),
.end_pa = addr_map_mc4_limit_r(),
.fake_registers = NULL,
.wlist = mc2to7_res_mss_mcf_wlist,
.wlist_size = ARRAY_SIZE(mc2to7_res_mss_mcf_wlist),
@@ -1299,8 +1300,8 @@ struct hwpm_resource_aperture mss_mcf_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC5_BASE,
.end_pa = NV_ADDRESS_MAP_MC5_LIMIT,
.start_pa = addr_map_mc5_base_r(),
.end_pa = addr_map_mc5_limit_r(),
.fake_registers = NULL,
.wlist = mc2to7_res_mss_mcf_wlist,
.wlist_size = ARRAY_SIZE(mc2to7_res_mss_mcf_wlist),
@@ -1308,8 +1309,8 @@ struct hwpm_resource_aperture mss_mcf_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC6_BASE,
.end_pa = NV_ADDRESS_MAP_MC6_LIMIT,
.start_pa = addr_map_mc6_base_r(),
.end_pa = addr_map_mc6_limit_r(),
.fake_registers = NULL,
.wlist = mc2to7_res_mss_mcf_wlist,
.wlist_size = ARRAY_SIZE(mc2to7_res_mss_mcf_wlist),
@@ -1317,8 +1318,8 @@ struct hwpm_resource_aperture mss_mcf_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MC7_BASE,
.end_pa = NV_ADDRESS_MAP_MC7_LIMIT,
.start_pa = addr_map_mc7_base_r(),
.end_pa = addr_map_mc7_limit_r(),
.fake_registers = NULL,
.wlist = mc2to7_res_mss_mcf_wlist,
.wlist_size = ARRAY_SIZE(mc2to7_res_mss_mcf_wlist),
@@ -1326,8 +1327,8 @@ struct hwpm_resource_aperture mss_mcf_map[] = {
.dt_aperture = TEGRA_SOC_HWPM_INVALID_DT,
},
{
.start_pa = NV_ADDRESS_MAP_MCB_BASE,
.end_pa = NV_ADDRESS_MAP_MCB_LIMIT,
.start_pa = addr_map_mcb_base_r(),
.end_pa = addr_map_mcb_limit_r(),
.fake_registers = NULL,
.wlist = mcb_res_mss_mcf_wlist,
.wlist_size = ARRAY_SIZE(mcb_res_mss_mcf_wlist),
@@ -1739,8 +1740,7 @@ static void fake_writel(struct tegra_soc_hwpm *hwpm,
/* Read a HWPM (PERFMON, PMA, or RTR) register */
u32 hwpm_readl(struct tegra_soc_hwpm *hwpm,
enum tegra_soc_hwpm_dt_aperture dt_aperture,
u32 reg)
enum tegra_soc_hwpm_dt_aperture dt_aperture, u32 reg_offset)
{
if ((dt_aperture < 0) ||
(dt_aperture >= TEGRA_SOC_HWPM_NUM_DT_APERTURES)) {
@@ -1748,8 +1748,8 @@ u32 hwpm_readl(struct tegra_soc_hwpm *hwpm,
return 0;
}
tegra_soc_hwpm_dbg("reg read: dt_aperture(%d), reg(0x%x)",
dt_aperture, reg);
tegra_soc_hwpm_dbg("reg read: dt_aperture(%d), reg_offset(0x%x)",
dt_aperture, reg_offset);
if (hwpm->fake_registers_enabled) {
u64 base_pa = 0;
@@ -1757,30 +1757,30 @@ u32 hwpm_readl(struct tegra_soc_hwpm *hwpm,
if (IS_PERFMON(dt_aperture))
base_pa = PERFMON_BASE(dt_aperture);
else if (dt_aperture == TEGRA_SOC_HWPM_PMA_DT)
base_pa = NV_ADDRESS_MAP_PMA_BASE;
base_pa = addr_map_pma_base_r();
else
base_pa = NV_ADDRESS_MAP_RTR_BASE;
base_pa = addr_map_rtr_base_r();
return fake_readl(hwpm, base_pa + reg);
return fake_readl(hwpm, base_pa + reg_offset);
} else {
return readl(hwpm->dt_apertures[dt_aperture] + reg);
return readl(hwpm->dt_apertures[dt_aperture] + reg_offset);
}
}
/* Write a HWPM (PERFMON, PMA, or RTR) register */
void hwpm_writel(struct tegra_soc_hwpm *hwpm,
enum tegra_soc_hwpm_dt_aperture dt_aperture,
u32 reg,
u32 val)
enum tegra_soc_hwpm_dt_aperture dt_aperture,
u32 reg_offset, u32 val)
{
if ((dt_aperture < 0) ||
(dt_aperture >= TEGRA_SOC_HWPM_NUM_DT_APERTURES)) {
(dt_aperture >= TEGRA_SOC_HWPM_NUM_DT_APERTURES)) {
tegra_soc_hwpm_err("Invalid dt aperture(%d)", dt_aperture);
return;
}
tegra_soc_hwpm_dbg("reg write: dt_aperture(%d), reg(0x%x), val(0x%x)",
dt_aperture, reg, val);
tegra_soc_hwpm_dbg(
"reg write: dt_aperture(%d), reg_offset(0x%x), val(0x%x)",
dt_aperture, reg_offset, val);
if (hwpm->fake_registers_enabled) {
u64 base_pa = 0;
@@ -1788,13 +1788,13 @@ void hwpm_writel(struct tegra_soc_hwpm *hwpm,
if (IS_PERFMON(dt_aperture))
base_pa = PERFMON_BASE(dt_aperture);
else if (dt_aperture == TEGRA_SOC_HWPM_PMA_DT)
base_pa = NV_ADDRESS_MAP_PMA_BASE;
base_pa = addr_map_pma_base_r();
else
base_pa = NV_ADDRESS_MAP_RTR_BASE;
base_pa = addr_map_rtr_base_r();
fake_writel(hwpm, base_pa + reg, val);
fake_writel(hwpm, base_pa + reg_offset, val);
} else {
writel(val, hwpm->dt_apertures[dt_aperture] + reg);
writel(val, hwpm->dt_apertures[dt_aperture] + reg_offset);
}
}
@@ -1867,9 +1867,8 @@ u32 ioctl_readl(struct tegra_soc_hwpm *hwpm,
if (aperture->is_ip) {
reg_val = ip_readl(hwpm, addr);
} else {
reg_val = hwpm_readl(hwpm,
aperture->dt_aperture,
addr - aperture->start_pa);
reg_val = hwpm_readl(hwpm, aperture->dt_aperture,
addr - aperture->start_pa);
}
return reg_val;
}
@@ -1891,10 +1890,8 @@ void ioctl_writel(struct tegra_soc_hwpm *hwpm,
if (aperture->is_ip) {
ip_writel(hwpm, addr, val);
} else {
hwpm_writel(hwpm,
aperture->dt_aperture,
addr - aperture->start_pa,
val);
hwpm_writel(hwpm, aperture->dt_aperture,
addr - aperture->start_pa, val);
}
}

46
tegra-soc-hwpm-io.h
View File

@@ -22,25 +22,6 @@
#include "tegra-soc-hwpm.h"
/* Mask and shift field_val so it can be written to a register */
#define HWPM_REG_F(field, field_val) \
(((field_val) << field##_SHIFT) & field##_MASK)
/* Extract a field's value from a register */
#define HWPM_REG_V(field, reg_val) \
(((reg_val) & field##_MASK) >> field##_SHIFT)
/*
* Check if field_val is set in reg_val. field_val is already masked and
* shifted to the correct location.
*/
#define HWPM_REG_CHECK(reg_val, field_mask, field_val) \
(((reg_val) & (field_mask)) == ((field_val) & (field_mask)))
/* Mask and shift field_val. Then check if field_val is set in reg_val. */
#define HWPM_REG_CHECK_F(reg_val, field, field_val) \
(((reg_val) & field##_MASK) == HWPM_REG_F(field, (field_val)))
struct whitelist {
u64 reg;
bool zero_in_init;
@@ -91,12 +72,11 @@ struct hwpm_resource_aperture *find_hwpm_aperture(struct tegra_soc_hwpm *hwpm,
u64 phys_addr,
bool check_reservation);
u32 hwpm_readl(struct tegra_soc_hwpm *hwpm,
enum tegra_soc_hwpm_dt_aperture dt_aperture,
u32 reg);
enum tegra_soc_hwpm_dt_aperture dt_aperture,
u32 reg_offset);
void hwpm_writel(struct tegra_soc_hwpm *hwpm,
enum tegra_soc_hwpm_dt_aperture dt_aperture,
u32 reg,
u32 val);
enum tegra_soc_hwpm_dt_aperture dt_aperture,
u32 reg_offset, u32 val);
u32 ip_readl(struct tegra_soc_hwpm *hwpm, u64 phys_addr);
void ip_writel(struct tegra_soc_hwpm *hwpm, u64 phys_addr, u32 val);
u32 ioctl_readl(struct tegra_soc_hwpm *hwpm,
@@ -114,23 +94,5 @@ int reg_rmw(struct tegra_soc_hwpm *hwpm,
u32 field_val,
bool is_ioctl,
bool is_ip);
#define DRIVER_REG_RMW(hwpm, dt_aperture, reg, field, field_val, is_ip) \
reg_rmw(hwpm, \
NULL, \
dt_aperture, \
reg, \
field##_MASK, \
HWPM_REG_F(field, field_val), \
false, \
is_ip)
#define IOCTL_REG_RMW(hwpm, aperture, addr, field_mask, field_val) \
reg_rmw(hwpm, \
aperture, \
aperture->dt_aperture, \
addr, \
field_mask, \
field_val, \
true, \
aperture->is_ip)
#endif /* TEGRA_SOC_HWPM_IO_H */

461
tegra-soc-hwpm-ioctl.c
View File

@@ -31,6 +31,10 @@
#include <uapi/linux/tegra-soc-hwpm-uapi.h>
#include "include/hw/t234/hw_pmasys_soc_hwpm.h"
#include "include/hw/t234/hw_pmmsys_soc_hwpm.h"
#include "include/hw/t234/hw_addr_map_soc_hwpm.h"
#include "tegra-soc-hwpm.h"
#include "tegra-soc-hwpm-io.h"
@@ -139,37 +143,37 @@ static u32 **get_mc_fake_regs(struct tegra_soc_hwpm *hwpm,
}
switch (aperture->start_pa) {
case NV_ADDRESS_MAP_MC0_BASE:
case addr_map_mc0_base_r():
return &mc_fake_regs[0];
case NV_ADDRESS_MAP_MC1_BASE:
case addr_map_mc1_base_r():
return &mc_fake_regs[1];
case NV_ADDRESS_MAP_MC2_BASE:
case addr_map_mc2_base_r():
return &mc_fake_regs[2];
case NV_ADDRESS_MAP_MC3_BASE:
case addr_map_mc3_base_r():
return &mc_fake_regs[3];
case NV_ADDRESS_MAP_MC4_BASE:
case addr_map_mc4_base_r():
return &mc_fake_regs[4];
case NV_ADDRESS_MAP_MC5_BASE:
case addr_map_mc5_base_r():
return &mc_fake_regs[5];
case NV_ADDRESS_MAP_MC6_BASE:
case addr_map_mc6_base_r():
return &mc_fake_regs[6];
case NV_ADDRESS_MAP_MC7_BASE:
case addr_map_mc7_base_r():
return &mc_fake_regs[7];
case NV_ADDRESS_MAP_MC8_BASE:
case addr_map_mc8_base_r():
return &mc_fake_regs[8];
case NV_ADDRESS_MAP_MC9_BASE:
case addr_map_mc9_base_r():
return &mc_fake_regs[9];
case NV_ADDRESS_MAP_MC10_BASE:
case addr_map_mc10_base_r():
return &mc_fake_regs[10];
case NV_ADDRESS_MAP_MC11_BASE:
case addr_map_mc11_base_r():
return &mc_fake_regs[11];
case NV_ADDRESS_MAP_MC12_BASE:
case addr_map_mc12_base_r():
return &mc_fake_regs[12];
case NV_ADDRESS_MAP_MC13_BASE:
case addr_map_mc13_base_r():
return &mc_fake_regs[13];
case NV_ADDRESS_MAP_MC14_BASE:
case addr_map_mc14_base_r():
return &mc_fake_regs[14];
case NV_ADDRESS_MAP_MC15_BASE:
case addr_map_mc15_base_r():
return &mc_fake_regs[15];
default:
return NULL;
@@ -188,99 +192,99 @@ static void set_mc_fake_regs(struct tegra_soc_hwpm *hwpm,
}
switch (aperture->start_pa) {
case NV_ADDRESS_MAP_MC0_BASE:
case addr_map_mc0_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[0];
mss_channel_map[0].fake_registers = fake_regs;
mss_iso_niso_hub_map[0].fake_registers = fake_regs;
mss_mcf_map[0].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC1_BASE:
case addr_map_mc1_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[1];
mss_channel_map[1].fake_registers = fake_regs;
mss_iso_niso_hub_map[1].fake_registers = fake_regs;
mss_mcf_map[1].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC2_BASE:
case addr_map_mc2_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[2];
mss_channel_map[2].fake_registers = fake_regs;
mss_iso_niso_hub_map[2].fake_registers = fake_regs;
mss_mcf_map[2].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC3_BASE:
case addr_map_mc3_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[3];
mss_channel_map[3].fake_registers = fake_regs;
mss_iso_niso_hub_map[3].fake_registers = fake_regs;
mss_mcf_map[3].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC4_BASE:
case addr_map_mc4_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[4];
mss_channel_map[4].fake_registers = fake_regs;
mss_iso_niso_hub_map[4].fake_registers = fake_regs;
mss_mcf_map[4].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC5_BASE:
case addr_map_mc5_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[5];
mss_channel_map[5].fake_registers = fake_regs;
mss_iso_niso_hub_map[5].fake_registers = fake_regs;
mss_mcf_map[5].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC6_BASE:
case addr_map_mc6_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[6];
mss_channel_map[6].fake_registers = fake_regs;
mss_iso_niso_hub_map[6].fake_registers = fake_regs;
mss_mcf_map[6].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC7_BASE:
case addr_map_mc7_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[7];
mss_channel_map[7].fake_registers = fake_regs;
mss_iso_niso_hub_map[7].fake_registers = fake_regs;
mss_mcf_map[7].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC8_BASE:
case addr_map_mc8_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[8];
mss_channel_map[8].fake_registers = fake_regs;
mss_iso_niso_hub_map[8].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC9_BASE:
case addr_map_mc9_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[9];
mss_channel_map[9].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC10_BASE:
case addr_map_mc10_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[10];
mss_channel_map[10].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC11_BASE:
case addr_map_mc11_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[11];
mss_channel_map[11].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC12_BASE:
case addr_map_mc12_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[12];
mss_channel_map[12].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC13_BASE:
case addr_map_mc13_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[13];
mss_channel_map[13].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC14_BASE:
case addr_map_mc14_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[14];
mss_channel_map[14].fake_registers = fake_regs;
break;
case NV_ADDRESS_MAP_MC15_BASE:
case addr_map_mc15_base_r():
fake_regs = (!hwpm->fake_registers_enabled || set_null) ?
NULL : mc_fake_regs[15];
mss_channel_map[15].fake_registers = fake_regs;
@@ -517,84 +521,61 @@ static int alloc_pma_stream_ioctl(struct tegra_soc_hwpm *hwpm,
}
hwpm->mem_bytes_kernel = dma_buf_vmap(hwpm->mem_bytes_dma_buf);
if (!hwpm->mem_bytes_kernel) {
tegra_soc_hwpm_err("Unable to map mem_bytes buffer into kernel VA space");
tegra_soc_hwpm_err(
"Unable to map mem_bytes buffer into kernel VA space");
ret = -ENOMEM;
goto fail;
}
memset(hwpm->mem_bytes_kernel, 0, 32);
outbase_lo = alloc_pma_stream->stream_buf_pma_va & 0xffffffffULL;
outbase_lo >>= NV_PERF_PMASYS_CHANNEL_OUTBASE_PTR_SHIFT;
reg_val = HWPM_REG_F(NV_PERF_PMASYS_CHANNEL_OUTBASE_PTR,
outbase_lo);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_OUTBASE_CH0,
reg_val);
outbase_lo = alloc_pma_stream->stream_buf_pma_va &
pmasys_channel_outbase_ptr_m();
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_outbase_r(0) - addr_map_pma_base_r(),
outbase_lo);
tegra_soc_hwpm_dbg("OUTBASE = 0x%x", reg_val);
outbase_hi = (alloc_pma_stream->stream_buf_pma_va >> 32) & 0xff;
outbase_hi >>= NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_PTR_SHIFT;
reg_val = HWPM_REG_F(NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_PTR,
outbase_hi);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_CH0,
reg_val);
outbase_hi = (alloc_pma_stream->stream_buf_pma_va >> 32) &
pmasys_channel_outbaseupper_ptr_m();
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_outbaseupper_r(0) - addr_map_pma_base_r(),
outbase_hi);
tegra_soc_hwpm_dbg("OUTBASEUPPER = 0x%x", reg_val);
outsize = alloc_pma_stream->stream_buf_size >>
NV_PERF_PMASYS_CHANNEL_OUTSIZE_NUMBYTES_SHIFT;
reg_val = HWPM_REG_F(NV_PERF_PMASYS_CHANNEL_OUTSIZE_NUMBYTES,
outsize);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_OUTSIZE_CH0,
reg_val);
outsize = alloc_pma_stream->stream_buf_size &
pmasys_channel_outsize_numbytes_m();
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_outsize_r(0) - addr_map_pma_base_r(),
outsize);
tegra_soc_hwpm_dbg("OUTSIZE = 0x%x", reg_val);
mem_bytes_addr = sg_dma_address(hwpm->mem_bytes_sgt->sgl) & 0xffffffffULL;
mem_bytes_addr >>= NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_PTR_SHIFT;
reg_val = HWPM_REG_F(NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_PTR,
mem_bytes_addr);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_CH0,
reg_val);
mem_bytes_addr = sg_dma_address(hwpm->mem_bytes_sgt->sgl) &
pmasys_channel_mem_bytes_addr_ptr_m();
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_mem_bytes_addr_r(0) - addr_map_pma_base_r(),
mem_bytes_addr);
tegra_soc_hwpm_dbg("MEM_BYTES_ADDR = 0x%x", reg_val);
reg_val = HWPM_REG_F(NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_VALID,
NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_VALID_TRUE);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_CH0,
reg_val);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_mem_block_r(0) - addr_map_pma_base_r(),
pmasys_channel_mem_block_valid_f(
pmasys_channel_mem_block_valid_true_v()));
return 0;
fail:
reg_val = HWPM_REG_F(NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_VALID,
NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_VALID_FALSE);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_MEM_BLOCK_CH0,
reg_val);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_OUTBASE_CH0,
0);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_CH0,
0);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_OUTSIZE_CH0,
0);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_CH0,
0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_mem_block_r(0) - addr_map_pma_base_r(),
pmasys_channel_mem_block_valid_f(
pmasys_channel_mem_block_valid_false_v()));
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_outbase_r(0) - addr_map_pma_base_r(), 0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_outbaseupper_r(0) - addr_map_pma_base_r(), 0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_outsize_r(0) - addr_map_pma_base_r(), 0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_mem_bytes_addr_r(0) - addr_map_pma_base_r(), 0);
alloc_pma_stream->stream_buf_pma_va = 0;
@@ -686,12 +667,12 @@ static int bind_ioctl(struct tegra_soc_hwpm *hwpm,
tegra_soc_hwpm_dbg("Found PERFMON(0x%llx - 0x%llx)",
aperture->start_pa,
aperture->end_pa);
ret = DRIVER_REG_RMW(hwpm,
aperture->dt_aperture,
NV_PERF_PMMSYS_SYS0_ENGINESTATUS,
NV_PERF_PMMSYS_SYS0_ENGINESTATUS_ENABLE,
NV_PERF_PMMSYS_SYS0_ENGINESTATUS_ENABLE_OUT,
false);
ret = reg_rmw(hwpm, NULL, aperture->dt_aperture,
pmmsys_sys0_enginestatus_r(0) -
addr_map_rpg_pm_base_r(),
pmmsys_sys0_enginestatus_enable_m(),
pmmsys_sys0_enginestatus_enable_out_f(),
false, false);
if (ret < 0) {
tegra_soc_hwpm_err("Unable to set PMM ENGINESTATUS_ENABLE"
" for PERFMON(0x%llx - 0x%llx)",
@@ -918,11 +899,9 @@ static int exec_reg_ops_ioctl(struct tegra_soc_hwpm *hwpm,
/* Read Modify Write operation */
case TEGRA_SOC_HWPM_REG_OP_CMD_WR32:
ret = IOCTL_REG_RMW(hwpm,
aperture,
reg_op->phys_addr,
reg_op->mask_lo,
reg_op->reg_val_lo);
ret = reg_rmw(hwpm, aperture, aperture->dt_aperture,
reg_op->phys_addr, reg_op->mask_lo,
reg_op->reg_val_lo, true, aperture->is_ip);
if (ret < 0) {
REG_OP_FAIL(INVALID,
"WR32 REGOP failed for register(0x%llx)",
@@ -935,11 +914,9 @@ static int exec_reg_ops_ioctl(struct tegra_soc_hwpm *hwpm,
/* Read Modify Write operation */
case TEGRA_SOC_HWPM_REG_OP_CMD_WR64:
/* Lower 32 bits */
ret = IOCTL_REG_RMW(hwpm,
aperture,
reg_op->phys_addr,
reg_op->mask_lo,
reg_op->reg_val_lo);
ret = reg_rmw(hwpm, aperture, aperture->dt_aperture,
reg_op->phys_addr, reg_op->mask_lo,
reg_op->reg_val_lo, true, aperture->is_ip);
if (ret < 0) {
REG_OP_FAIL(INVALID,
"WR64 REGOP failed for register(0x%llx)",
@@ -948,11 +925,9 @@ static int exec_reg_ops_ioctl(struct tegra_soc_hwpm *hwpm,
}
/* Upper 32 bits */
ret = IOCTL_REG_RMW(hwpm,
aperture,
reg_op->phys_addr + 4,
reg_op->mask_hi,
reg_op->reg_val_hi);
ret = reg_rmw(hwpm, aperture, aperture->dt_aperture,
reg_op->phys_addr + 4, reg_op->mask_hi,
reg_op->reg_val_hi, true, aperture->is_ip);
if (ret < 0) {
REG_OP_FAIL(INVALID,
"WR64 REGOP failed for register(0x%llx)",
@@ -997,21 +972,19 @@ static int update_get_put_ioctl(struct tegra_soc_hwpm *hwpm,
}
/* Update SW get pointer */
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_MEM_BUMP_CH0,
update_get_put->mem_bump);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_mem_bump_r(0) - addr_map_pma_base_r(),
update_get_put->mem_bump);
/* Stream MEM_BYTES value to MEM_BYTES buffer */
if (update_get_put->b_stream_mem_bytes) {
mem_bytes_kernel_u32 = (u32 *)(hwpm->mem_bytes_kernel);
*mem_bytes_kernel_u32 = TEGRA_SOC_HWPM_MEM_BYTES_INVALID;
ret = DRIVER_REG_RMW(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_CONTROL_USER_CH0,
NV_PERF_PMASYS_CHANNEL_CONTROL_USER_UPDATE_BYTES,
NV_PERF_PMASYS_CHANNEL_CONTROL_USER_UPDATE_BYTES_DOIT,
false);
ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_control_user_r(0) - addr_map_pma_base_r(),
pmasys_channel_control_user_update_bytes_m(),
pmasys_channel_control_user_update_bytes_doit_f(),
false, false);
if (ret < 0) {
tegra_soc_hwpm_err("Failed to stream mem_bytes to buffer");
return -EIO;
@@ -1020,25 +993,22 @@ static int update_get_put_ioctl(struct tegra_soc_hwpm *hwpm,
/* Read HW put pointer */
if (update_get_put->b_read_mem_head) {
update_get_put->mem_head =
hwpm_readl(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_MEM_HEAD_CH0);
update_get_put->mem_head = hwpm_readl(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_mem_head_r(0) - addr_map_pma_base_r());
tegra_soc_hwpm_dbg("MEM_HEAD = 0x%llx",
update_get_put->mem_head);
}
/* Check overflow error status */
if (update_get_put->b_check_overflow) {
reg_val = hwpm_readl(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_CH0);
field_val =
HWPM_REG_V(NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_MEMBUF_STATUS,
reg_val);
update_get_put->b_overflowed =
(field_val ==
NV_PERF_PMASYS_CHANNEL_STATUS_SECURE_MEMBUF_STATUS_OVERFLOWED);
reg_val = hwpm_readl(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_status_secure_r(0) -
addr_map_pma_base_r());
field_val = pmasys_channel_status_secure_membuf_status_v(
reg_val);
update_get_put->b_overflowed = (field_val ==
pmasys_channel_status_secure_membuf_status_overflowed_v());
tegra_soc_hwpm_dbg("OVERFLOWED = %u",
update_get_put->b_overflowed);
}
@@ -1264,23 +1234,21 @@ static int tegra_soc_hwpm_open(struct inode *inode, struct file *filp)
/* FIXME: Remove after verification */
/* Disable SLCG */
ret = DRIVER_REG_RMW(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CG2,
NV_PERF_PMASYS_CG2_SLCG,
NV_PERF_PMASYS_CG2_SLCG_DISABLED,
false);
ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT,
pmasys_cg2_r() - addr_map_pma_base_r(),
pmasys_cg2_slcg_m(), pmasys_cg2_slcg_disabled_f(),
false, false);
if (ret < 0) {
tegra_soc_hwpm_err("Unable to disable PMA SLCG");
ret = -EIO;
goto fail;
}
ret = DRIVER_REG_RMW(hwpm,
TEGRA_SOC_HWPM_RTR_DT,
NV_PERF_PMMSYS_SYS0ROUTER_CG2,
NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG,
NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_DISABLED,
false);
ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_RTR_DT,
pmmsys_sys0router_cg2_r() - addr_map_rtr_base_r(),
pmmsys_sys0router_cg2_slcg_m(),
pmmsys_sys0router_cg2_slcg_disabled_f(),
false, false);
if (ret < 0) {
tegra_soc_hwpm_err("Unable to disable ROUTER SLCG");
ret = -EIO;
@@ -1288,23 +1256,22 @@ static int tegra_soc_hwpm_open(struct inode *inode, struct file *filp)
}
/* Program PROD values */
ret = DRIVER_REG_RMW(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CONTROLB,
NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES,
NV_PERF_PMASYS_CONTROLB_COALESCE_TIMEOUT_CYCLES__PROD,
false);
ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT,
pmasys_controlb_r() - addr_map_pma_base_r(),
pmasys_controlb_coalesce_timeout_cycles_m(),
pmasys_controlb_coalesce_timeout_cycles__prod_f(),
false, false);
if (ret < 0) {
tegra_soc_hwpm_err("Unable to program PROD value");
ret = -EIO;
goto fail;
}
ret = DRIVER_REG_RMW(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_CONFIG_USER_CH0,
NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES,
NV_PERF_PMASYS_CHANNEL_CONFIG_USER_COALESCE_TIMEOUT_CYCLES__PROD,
false);
ret = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_config_user_r(0) - addr_map_pma_base_r(),
pmasys_channel_config_user_coalesce_timeout_cycles_m(),
pmasys_channel_config_user_coalesce_timeout_cycles__prod_f(),
false, false);
if (ret < 0) {
tegra_soc_hwpm_err("Unable to program PROD value");
ret = -EIO;
@@ -1394,62 +1361,50 @@ static int tegra_soc_hwpm_release(struct inode *inode, struct file *filp)
}
/* Disable PMA triggers */
err = DRIVER_REG_RMW(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_TRIGGER_CONFIG_USER_CH0,
NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE,
NV_PERF_PMASYS_TRIGGER_CONFIG_USER_PMA_PULSE_DISABLE,
false);
err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT,
pmasys_trigger_config_user_r(0) - addr_map_pma_base_r(),
pmasys_trigger_config_user_pma_pulse_m(),
pmasys_trigger_config_user_pma_pulse_disable_f(),
false, false);
RELEASE_FAIL("Unable to disable PMA triggers");
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_SYS_TRIGGER_START_MASK,
0);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_SYS_TRIGGER_START_MASKB,
0);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASK,
0);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_SYS_TRIGGER_STOP_MASKB,
0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_sys_trigger_start_mask_r() - addr_map_pma_base_r(), 0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_sys_trigger_start_maskb_r() - addr_map_pma_base_r(), 0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_sys_trigger_stop_mask_r() - addr_map_pma_base_r(), 0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_sys_trigger_stop_maskb_r() - addr_map_pma_base_r(), 0);
/* Wait for PERFMONs, ROUTER, and PMA to idle */
timeout = HWPM_TIMEOUT(HWPM_REG_CHECK_F(hwpm_readl(hwpm,
TEGRA_SOC_HWPM_RTR_DT,
NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS),
NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED,
NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED_EMPTY),
"NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED_EMPTY");
timeout = HWPM_TIMEOUT(pmmsys_sys0router_perfmonstatus_merged_v(
hwpm_readl(hwpm, TEGRA_SOC_HWPM_RTR_DT,
pmmsys_sys0router_perfmonstatus_r() -
addr_map_rtr_base_r())) == 0U,
"NV_PERF_PMMSYS_SYS0ROUTER_PERFMONSTATUS_MERGED_EMPTY");
if (timeout && ret == 0) {
ret = -EIO;
}
timeout = HWPM_TIMEOUT(HWPM_REG_CHECK_F(hwpm_readl(hwpm,
TEGRA_SOC_HWPM_RTR_DT,
NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS),
NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS,
NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_EMPTY),
"NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_EMPTY");
timeout = HWPM_TIMEOUT(pmmsys_sys0router_enginestatus_status_v(
hwpm_readl(hwpm, TEGRA_SOC_HWPM_RTR_DT,
pmmsys_sys0router_enginestatus_r() -
addr_map_rtr_base_r())) ==
pmmsys_sys0router_enginestatus_status_empty_v(),
"NV_PERF_PMMSYS_SYS0ROUTER_ENGINESTATUS_STATUS_EMPTY");
if (timeout && ret == 0) {
ret = -EIO;
}
field_mask = NV_PERF_PMASYS_ENGINESTATUS_STATUS_MASK |
NV_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY_MASK;
field_val = HWPM_REG_F(NV_PERF_PMASYS_ENGINESTATUS_STATUS,
NV_PERF_PMASYS_ENGINESTATUS_STATUS_EMPTY);
field_val |= HWPM_REG_F(NV_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY,
NV_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY_EMPTY);
timeout = HWPM_TIMEOUT(HWPM_REG_CHECK(hwpm_readl(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_ENGINESTATUS),
field_mask,
field_val),
"NV_PERF_PMASYS_ENGINESTATUS");
field_mask = pmasys_enginestatus_status_m() |
pmasys_enginestatus_rbufempty_m();
field_val = pmasys_enginestatus_status_empty_f() ||
pmasys_enginestatus_rbufempty_empty_f();
timeout = HWPM_TIMEOUT((hwpm_readl(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_enginestatus_r() -
addr_map_pma_base_r()) & field_mask) == field_val,
"NV_PERF_PMASYS_ENGINESTATUS");
if (timeout && ret == 0) {
ret = -EIO;
}
@@ -1469,12 +1424,11 @@ static int tegra_soc_hwpm_release(struct inode *inode, struct file *filp)
tegra_soc_hwpm_dbg("Found PERFMON(0x%llx - 0x%llx)",
aperture->start_pa,
aperture->end_pa);
err = DRIVER_REG_RMW(hwpm,
aperture->dt_aperture,
NV_PERF_PMMSYS_CONTROL,
NV_PERF_PMMSYS_CONTROL_MODE,
NV_PERF_PMMSYS_CONTROL_MODE_DISABLE,
false);
err = reg_rmw(hwpm, NULL, aperture->dt_aperture,
pmmsys_control_r(0) - addr_map_rpg_pm_base_r(),
pmmsys_control_mode_m(),
pmmsys_control_mode_disable_f(),
false, false);
RELEASE_FAIL("Unable to disable PERFMON(0x%llx - 0x%llx)",
aperture->start_pa,
aperture->end_pa);
@@ -1486,12 +1440,11 @@ static int tegra_soc_hwpm_release(struct inode *inode, struct file *filp)
if (hwpm->mem_bytes_kernel) {
mem_bytes_kernel_u32 = (u32 *)(hwpm->mem_bytes_kernel);
*mem_bytes_kernel_u32 = TEGRA_SOC_HWPM_MEM_BYTES_INVALID;
err = DRIVER_REG_RMW(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_CONTROL_USER_CH0,
NV_PERF_PMASYS_CHANNEL_CONTROL_USER_UPDATE_BYTES,
NV_PERF_PMASYS_CHANNEL_CONTROL_USER_UPDATE_BYTES_DOIT,
false);
err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_control_user_r(0) - addr_map_pma_base_r(),
pmasys_channel_control_user_update_bytes_m(),
pmasys_channel_control_user_update_bytes_doit_f(),
false, false);
RELEASE_FAIL("Unable to stream MEM_BYTES");
timeout = HWPM_TIMEOUT(*mem_bytes_kernel_u32 !=
TEGRA_SOC_HWPM_MEM_BYTES_INVALID,
@@ -1501,38 +1454,29 @@ static int tegra_soc_hwpm_release(struct inode *inode, struct file *filp)
}
/* Disable PMA streaming */
err = DRIVER_REG_RMW(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_TRIGGER_CONFIG_USER_CH0,
NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RECORD_STREAM,
NV_PERF_PMASYS_TRIGGER_CONFIG_USER_RECORD_STREAM_DISABLE,
false);
err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT,
pmasys_trigger_config_user_r(0) - addr_map_pma_base_r(),
pmasys_trigger_config_user_record_stream_m(),
pmasys_trigger_config_user_record_stream_disable_f(),
false, false);
RELEASE_FAIL("Unable to disable PMA streaming");
err = DRIVER_REG_RMW(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_CONTROL_USER_CH0,
NV_PERF_PMASYS_CHANNEL_CONTROL_USER_STREAM,
NV_PERF_PMASYS_CHANNEL_CONTROL_USER_STREAM_DISABLE,
false);
err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_control_user_r(0) - addr_map_pma_base_r(),
pmasys_channel_control_user_stream_m(),
pmasys_channel_control_user_stream_disable_f(),
false, false);
RELEASE_FAIL("Unable to disable PMA streaming");
/* Memory Management */
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_OUTBASE_CH0,
0);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_OUTBASEUPPER_CH0,
0);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_OUTSIZE_CH0,
0);
hwpm_writel(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CHANNEL_MEM_BYTES_ADDR_CH0,
0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_outbase_r(0) - addr_map_pma_base_r(), 0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_outbaseupper_r(0) - addr_map_pma_base_r(), 0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_outsize_r(0) - addr_map_pma_base_r(), 0);
hwpm_writel(hwpm, TEGRA_SOC_HWPM_PMA_DT,
pmasys_channel_mem_bytes_addr_r(0) - addr_map_pma_base_r(), 0);
if (hwpm->stream_sgt && (!IS_ERR(hwpm->stream_sgt))) {
dma_buf_unmap_attachment(hwpm->stream_attach,
@@ -1586,19 +1530,16 @@ static int tegra_soc_hwpm_release(struct inode *inode, struct file *filp)
/* FIXME: Remove after verification */
/* Enable SLCG */
err = DRIVER_REG_RMW(hwpm,
TEGRA_SOC_HWPM_PMA_DT,
NV_PERF_PMASYS_CG2,
NV_PERF_PMASYS_CG2_SLCG,
NV_PERF_PMASYS_CG2_SLCG_ENABLED,
false);
err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_PMA_DT,
pmasys_cg2_r() - addr_map_pma_base_r(),
pmasys_cg2_slcg_m(),
pmasys_cg2_slcg_enabled_f(), false, false);
RELEASE_FAIL("Unable to enable PMA SLCG");
err = DRIVER_REG_RMW(hwpm,
TEGRA_SOC_HWPM_RTR_DT,
NV_PERF_PMMSYS_SYS0ROUTER_CG2,
NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG,
NV_PERF_PMMSYS_SYS0ROUTER_CG2_SLCG_ENABLED,
false);
err = reg_rmw(hwpm, NULL, TEGRA_SOC_HWPM_RTR_DT,
pmmsys_sys0router_cg2_r() - addr_map_rtr_base_r(),
pmmsys_sys0router_cg2_slcg_m(),
pmmsys_sys0router_cg2_slcg_enabled_f(), false, false);
RELEASE_FAIL("Unable to enable ROUTER SLCG");
/* Unmap PMA and RTR apertures */
@@ -1632,7 +1573,6 @@ static int tegra_soc_hwpm_release(struct inode *inode, struct file *filp)
for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) {
if (!hwpm_resources[res_idx].reserved)
continue;
tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx);
hwpm_resources[res_idx].reserved = false;
for (aprt_idx = 0;
@@ -1665,7 +1605,6 @@ static int tegra_soc_hwpm_release(struct inode *inode, struct file *filp)
}
}
}
return ret;
}