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tegra: hwpm: th500: fixes and reorg of IPs

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This patch fixes issues found during testing
and guidance provided by devtools. The following
is changed in this patch:

1. mcf_iobhx and mcf_ocu are merged into a single mcf_soc IP.
2a. c2c is changed from 2 instances to 1.
2b. Remove C2CS0/1 which are the broadcast apertures.
    Also remove the allowlist offset specific to broadcast
    aperture.
3. mss_hub is changed from 1 instance to 8.
4. mss_channel is changed from 1 instance to 32.
5. mc0 perfmux is added to mcf_clink.
6. mcf_core is changed from 1 instance to 8.
7. License headers updated where necessary.
8. c2c allowlist updated to have just the offsets common
   to all links.
9. Added a verbose comment explaining the design of
   th500_hwpm_force_enable_ips()
10. Added back validate_current_config module parameter
    as many systems still don't support fuses.
11. If all F's are read back for a regop in ip_readl(),
    return -ENODEV.

There is a corresponding patch to update the python scripts
that generated many of the C and header files.

Bug 4287384

Change-Id: I8e14b0165dfa1abb9f5e04de577a41f0eb278246
Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3134365
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Eric Lu <ericlu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Vishal Aslot
2024-05-09 04:56:05 -07:00
committed by mobile promotions
parent fdbe788448
commit cdbd6e7a24
27 changed files with 4716 additions and 1004 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/tegra/hwpm/os/linux/debugfs.c
View File

@@ -25,7 +25,6 @@
void tegra_hwpm_debugfs_init(struct tegra_hwpm_os_linux *hwpm_linux)
{
struct tegra_soc_hwpm *hwpm = &hwpm_linux->hwpm;
extern int dbg_mask;
if (!hwpm_linux) {
tegra_hwpm_err(hwpm, "Invalid hwpm_linux struct");
@@ -43,8 +42,6 @@ void tegra_hwpm_debugfs_init(struct tegra_hwpm_os_linux *hwpm_linux)
debugfs_create_u32("log_mask", S_IRUGO|S_IWUSR,
hwpm_linux->debugfs_root, &hwpm->dbg_mask);
hwpm->dbg_mask = ((u32)dbg_mask & hwpm_dbg_all_bits);
return;
fail:

91
drivers/tegra/hwpm/os/linux/driver.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: GPL-2.0-only
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -10,8 +9,6 @@
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifdef CONFIG_TEGRA_HWPM_OOT
#include <nvidia/conftest.h>
@@ -19,13 +16,11 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/moduleparam.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/dma-buf.h>
#include <linux/debugfs.h>
#include <linux/stat.h>
#include <tegra_hwpm.h>
#include <tegra_hwpm_ip.h>
@@ -38,68 +33,6 @@
#include <os/linux/driver.h>
#include <os/linux/acpi.h>
/*
* Optional module parameters
*/
#define S_IRWUG (S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP)
/* Debug mask at driver load time. Can be overridden via debugfs later */
int dbg_mask = 0;
module_param(dbg_mask, int, S_IRWUG);
/* This is a WAR on TH500 */
int validate_current_config = 1;
module_param(validate_current_config, int, S_IRWUG);
/*
* IP software masks to be used for force-enablement.
* 0x0 means "do not force-enable"
*/
long int nvlctrl_mask = 0x0;
module_param(nvlctrl_mask, long, S_IRWUG);
long int nvlrx_mask = 0x0;
module_param(nvlrx_mask, long, S_IRWUG);
long int nvltx_mask = 0x0;
module_param(nvltx_mask, long, S_IRWUG);
long int c2c_mask = 0x0;
module_param(c2c_mask, long, S_IRWUG);
long int cl2_mask = 0x0;
module_param(cl2_mask, long, S_IRWUG);
long int mcf_c2c_mask = 0x0;
module_param(mcf_c2c_mask, long, S_IRWUG);
long int mcf_clink_mask = 0x0;
module_param(mcf_clink_mask, long, S_IRWUG);
long int mcf_core_mask = 0x0;
module_param(mcf_core_mask, long, S_IRWUG);
long int mcf_iobhx_mask = 0x0;
module_param(mcf_iobhx_mask, long, S_IRWUG);
long int mcf_ocu_mask = 0x0;
module_param(mcf_ocu_mask, long, S_IRWUG);
long int mss_channel_mask = 0x0;
module_param(mss_channel_mask, long, S_IRWUG);
long int mss_hub_mask = 0x0;
module_param(mss_hub_mask, long, S_IRWUG);
long int pcie_mask = 0x0;
module_param(pcie_mask, long, S_IRWUG);
long int smmu_mask = 0x0;
module_param(smmu_mask, long, S_IRWUG);
/* Socket number */
int socket_number = 0x0;
static const struct of_device_id tegra_soc_hwpm_of_match[] = {
{
.compatible = "nvidia,t234-soc-hwpm",
@@ -117,26 +50,6 @@ static const struct of_device_id tegra_soc_hwpm_of_match[] = {
};
MODULE_DEVICE_TABLE(of, tegra_soc_hwpm_of_match);
/*
* The socket number must be 0, 1, 2, or 3.
*/
static int set_socket_number(const char *val, const struct kernel_param *kp)
{
int socket_num = 0, ret;
ret = kstrtoint(val, 10, &socket_num);
if (ret != 0 || socket_num < 0 || socket_num > 3)
return -EINVAL;
return param_set_int(val, kp);
}
static const struct kernel_param_ops param_ops = {
.set = set_socket_number,
.get = param_get_int,
};
module_param_cb(socket, &param_ops, &socket_number, S_IRWUG | S_IROTH);
#if defined(NV_CLASS_STRUCT_DEVNODE_HAS_CONST_DEV_ARG)
static char *tegra_hwpm_get_devnode(const struct device *dev, umode_t *mode)
#else

11
drivers/tegra/hwpm/os/linux/io_utils.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: GPL-2.0-only
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -10,8 +9,6 @@
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/slab.h>
@@ -147,6 +144,10 @@ static int ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
}
*val = __raw_readl(ptr);
iounmap(ptr);
/* If all F's received, it's a failure */
if (*val == 0xFFFFFFFFU)
return -ENODEV;
}
}
return 0;

21
drivers/tegra/hwpm/os/linux/ip_utils.c
View File

@@ -1,6 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: GPL-2.0-only
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -10,8 +9,6 @@
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/slab.h>
@@ -108,11 +105,8 @@ static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm,
case TEGRA_SOC_HWPM_IP_MSS_HUB:
ip_enum_idx = TEGRA_HWPM_IP_MSS_HUB;
break;
case TEGRA_SOC_HWPM_IP_MCF_OCU:
ip_enum_idx = TEGRA_HWPM_IP_MCF_OCU;
break;
case TEGRA_SOC_HWPM_IP_MCF_IOBHX:
ip_enum_idx = TEGRA_HWPM_IP_MCF_IOBHX;
case TEGRA_SOC_HWPM_IP_MCF_SOC:
ip_enum_idx = TEGRA_HWPM_IP_MCF_SOC;
break;
case TEGRA_SOC_HWPM_IP_MCF_C2C:
ip_enum_idx = TEGRA_HWPM_IP_MCF_C2C;
@@ -255,11 +249,8 @@ u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm,
case TEGRA_SOC_HWPM_RESOURCE_MSS_HUB:
res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_HUB;
break;
case TEGRA_SOC_HWPM_RESOURCE_MCF_OCU:
res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_OCU;
break;
case TEGRA_SOC_HWPM_RESOURCE_MCF_IOBHX:
res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_IOBHX;
case TEGRA_SOC_HWPM_RESOURCE_MCF_SOC:
res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_SOC;
break;
case TEGRA_SOC_HWPM_RESOURCE_MCF_C2C:
res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_C2C;