HWPM driver uses nested structures and arrays of structures. The IP
structure setup logic allocates pointer arrays based on dynamic list of
IPs and aperture addresses. This dynamic list is required to search
given regops address in less amount of time.
However, there is a chance that the number of pointers computed
dynamically is huge. And huge amount of memory will be required for the
dynamic pointers array, which is impractical.
This, this patch modifies ip structure setup and address to aperture
conversion logic to use static indexes if the pointer array size is
huge.
This patch modifies relevant functions to always use static arrays
to access instance and aperture structures.
If dynamic pointers array is allocated, the patch adds logic to
translate dynamic index to static index using inst_index_mask for
instances and new added aperture_index for element level structures.
Add/update few log message to improve relayed information.
Bug 4707244
Change-Id: Ib4847e6575f82b628a3ce838ad69196a4bc08fed
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3186843
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This patch fixes issues found during testing
and guidance provided by devtools. The following
is changed in this patch:
1. mcf_iobhx and mcf_ocu are merged into a single mcf_soc IP.
2a. c2c is changed from 2 instances to 1.
2b. Remove C2CS0/1 which are the broadcast apertures.
Also remove the allowlist offset specific to broadcast
aperture.
3. mss_hub is changed from 1 instance to 8.
4. mss_channel is changed from 1 instance to 32.
5. mc0 perfmux is added to mcf_clink.
6. mcf_core is changed from 1 instance to 8.
7. License headers updated where necessary.
8. c2c allowlist updated to have just the offsets common
to all links.
9. Added a verbose comment explaining the design of
th500_hwpm_force_enable_ips()
10. Added back validate_current_config module parameter
as many systems still don't support fuses.
11. If all F's are read back for a regop in ip_readl(),
return -ENODEV.
There is a corresponding patch to update the python scripts
that generated many of the C and header files.
Bug 4287384
Change-Id: I8e14b0165dfa1abb9f5e04de577a41f0eb278246
Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3134365
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Eric Lu <ericlu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
A recent change has led to EMC fuse mask calculation regression.
This is being corrected in this patch. The emc_fuse_disable mask
is set in such a way that, each bit corresponds to 4 MSS Channels.
For example, emc_fuse_disable mask=1100, corresponds to MSS_Channel0
to MSS_Channel7 being present, while MSS_Channel8 to MSS_Channel15
are floorswept. However, in HWPM Driver, the logic to represent a
floorswept IP element is indicated by '1'. Correct the logic to
indicate this.
Bug 4490868
Change-Id: Id83d9e1d983c3fbf8f58cef3a1ff45334d7eadd6
Signed-off-by: vasukis <vasukis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3122752
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
A recent change has led to EMC fuse mask calculation regression.
This is being corrected in this patch. The emc_fuse_disable mask is
set in such a way that, each bit corresponds to 4 MSS Channels.
For example, emc_fuse_disable mask=1100, corresponds to MSS_Channel0
to MSS_Channel7 being present, while MSS_Channel8 to MSS_Channel15
are floorswept. However, in HWPM Driver, the logic to represent
a floorswept IP element is indicated by '1'. Correct the logic to
indicate this.
Bug 4490868
Signed-off-by: vasukis <vasukis@nvidia.com>
Change-Id: Ia3825db29715e04aa43822283b160252d00f0a81
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3099298
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This patch adds support for MCF SOC performance
monitoring in the driver. MCF SOC has two different
types of perfmuxes connected to the same perfmon:
one is the OCU type and the other is IBHX and OBHX.
IBHX is only accessible via MC16 aperture. Therefore,
this patch adds two separate IPs: OCU and IOBHX.
However, both are tied to the MCF SOC perfmon (mcfsoc0).
Bug 4287384
Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Change-Id: If15498a44e02270f9106337078931edbe043c254
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2986232
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
This patch adds support for C-NVLINK performance
monitoring in the driver. C-NVLINK consists of
RX, TX, and CTRL apertures, each with its own
perfmux signals and perfmons. So this patch
breaks them up into three sets of perfmux-perfmon
data structures.
Bug 4287384
Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Change-Id: Id8be4c965018125765f75a7b8bc8ab809bb7f976
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2999166
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
HWPM resource manager in QNX will query register read/write
ops to the IP debug node exposed. This is done via devctl
calls from the HWPM Res Mgr. Hence, update the NVDEC debug
node name in ip source file.
Bug 4170733
DOS-SHR-7601
Change-Id: I817aa18be43534907d761c992b9953918a39525d
Signed-off-by: vasukis <vasukis@nvidia.com>
(cherry picked from commit 7ed60c287e1253b834bfe050952240e97549e320)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2991341
Reviewed-by: Vishal Aslot <vaslot@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- HALs get_rtr_int_idx and get_ip_max_idx return the chip specific
router index and number of IPs. This information is static for a chip
and doesn't require any input. Hence, update the HAL definition to not
require hwpm pointer as an argument. Update definition and references
for these HALs.
- Add new HAL to get PMA and RTR structure pointers. Implement and
update other chip specific functions to use new HAL.
- Add new timer macro to check a condition and timeout after given
retries. Update necessary code to use new timer macro.
- Correct validate_emc_config function to compute correct available mss
channel mask based on fuse value.
- Update tegra_hwpm_readl and tegra_hwpm_writel macros to assert error
value. This way error checks are added at one spot and not sprinkled all
over the driver code.
- Update get_mem_bytes_put_ptr() and membuf_overflow_status() to return
error as function return and accept arguments to return mem_head pointer
and overflow status respectively. Add overflow status macros to use
throughout driver. Update HAL definition and references accordingly.
- conftest is only compiled for OOT config atm. Add OOT config check to
include conftest header.
Jira THWPM-109
Change-Id: I77d150e860fa344a1604d241e27718150fdb8647
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2982555
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Vishal Aslot <vaslot@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
HWPM resource manager in QNX will query register read/write
ops to the IP debug nodes exposed. This is done via devctl
calls from the HWPM Res Mgr. Hence, update the IP debug node
names in ip souce files.
Bug 4170733
DOS-SHR-7601
Change-Id: I58a39305aa8d6fcbbe01494d1e18069a369ee46f
Signed-off-by: vasukis <vasukis@nvidia.com>
(cherry picked from commit d37297cb494bb6bfc3b531e38302de18d0fddfc5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2985248
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
On production board, MC config details are available through fuses. Add
function to read MC config fuse. Use the floorsweep fuse info to find
available elements.
Bug 3936487
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: I9e1549e3dfb9c06d8013ca2e1d43eb21bf0289f4
(cherry picked from commit f38e98a94ab8d478af3ebe1c922da606df9b67dc)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2888554
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Modify OS agnostic files in common, hal and include folder to use MIT
license. This will allow the files to be shared between different OSes.
Modify OS specific files in os/linux and uapi folders to add SPDX
identifier for GPLv2.
Jira THWPM-69
Change-Id: I4fef142354a46fc23b67616204ccf0712a99caec
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797453
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
HWPM components (PMA, RTR, perfmon) have MMIO address space and a
corresponding virtual address region. It is possible that both MMIO and
virtual addresses are same for an aperture.
MMIO address of an aperture is used in device node to enable the
aperture and further to map HWPM component in the driver.
Virtual addresses are used by the applications to execute regops on HWPM
apertures. Virtual addresses are also used to fake aperture address
space in simulation.
This patch updates
- HWPM aperture structures to include MMIO address.
- aperture ioremap function to use MMIO address values.
- fake register allocation to use virtual address values.
Jira THWPM-41
Change-Id: I05acb68dcb278722cd333e1187b2355d1d739e93
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
(cherry picked from commit 1c0e8107b4cddad7532c10dddc22bb30cef2540b)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2853213
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- HWPM driver requires to know if an IP is available for performance
measurements. The ideal way is for IP driver registration with HWPM
driver. This way IP driver can share required power management and
register access function pointers.
- For IPs that do not have registration mechanism implemented, a
workaround to set an IP enabled is implemented in the HWPM driver.
- In the recent releases, MSS channel, PVA and DLA IPs are the only PORs
for production builds. Currently, this is acheived using the combination
of minimal build and force enable flags.
- However, this implementation limits the number of enabled IPs on TOT
to only minimal expected ones.
- This patch modifies the force enable IP logic implementation to make
force enable and minimal IP flag definition more clear.
- CONFIG_T234_HWPM_ALLOW_FORCE_ENABLE should be used to purposely enable
IPs that do not have registration mechanism implemented. This flag is
used for POR or non-POR IPs. Ideally, all IPs should implement HWPM
registration and force enable flag should not be required.
- CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE should be used to implement logic
for POR IPs. In other words, if CONFIG_TEGRA_HWPM_MINIMAL_IP_ENABLE is
not defined, non-POR IPs should be included in the builds. This patch
sets MINIMAL IP config only for external non-safety builds.
- Fix include t234_perfmon_device_index.h error in t234_mss_mcf.c file.
- Add missing device index for PVA perfmon C0.
Jira THWPM-41
Change-Id: I20651eac14b6d42e5bf3cc5164d1f64ec208dc04
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2818735
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Add Device_index tag to read IP perfmon register address
index from ACPI or DTSI tables. Device_index will be
used to retrieve resource information from acpi tables
or device trees. This will replace current logic to
procure resource details using device names.
JIRA THWPM-71
Change-Id: I964546f2262dd77ec0acfb58f49d044c870deae6
Signed-off-by: vasukis <vasukis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797448
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Tested-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Currently, dt_index aperture spec actually holds the element index of
the aperture within the IP instance. Hence, replace dt_index with
element_index to better indicate its purpose.
JIRA THWPM-71
Change-Id: Ic805da3281c60991e7966a80f442d84a2cfcf7cc
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797447
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
- Make clock reset functions into HALs. This way we can control
clock-reset logic for any chip. Set clock-reset HAL pointers to
appropriate functions.
- Remove clock-reset function wrappers as these will not be required and
corresponding HAL pointers will be used.
- As clock reset init is defined as a HAL, modify probe logic to
initialize chip info before invoking any HALs.
- Move common/primary HAL validation logic to common code and implement
new HAL to validate chip specific HALs. This way we can ensure that HAL
pointers are set as expected.
- Keep only one definition for t234_hwpm_init_chip_info as t234 should
always be initialized and hence only single definition should be
available.
- Expected return value of 0 indicates success and any other value
(mostly negative in current logic) indicates error, compare function
returns with 0 to print error in tegra_hwpm_release().
- Since a build can support both ACPI and device tree, update
init_chip_info() to retrieve chip information from ACPI and device tree
in case of failure.
Jira THWPM-41
Bug 3583624
Change-Id: I03fefae0b3b0c8ce46d175d39e4fdbb45e2bb22f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2789668
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797445
- Zeroing of PMA trigger registers is unnecessary. Remove corresponding
logic from HWPM teardown function.
- During device open, add a check for PMA/RTR status. This will ensure
that PMA/RTR are ready to start new profiling session. Device open will
fail if RTR and PMA enginestatus is not ready(idle).
- SOC HWPM driver disables and releases all reserved IPs before teardown
steps. Update teardown logic to zero out IP allowlist registers during
teardown.
Jira THWPM-41
Bug 3714516
Change-Id: Iede5a5ed9860e2a73c8e4a04aeedfc061458c793
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2776229
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797444
HWPM files are copied from the previous source in linux-nvidia repo
withgit history. Create folders and move files to obtain expected folder
structure.
Bug 3787076
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
