Floorsweep info ioctl shares flattened IP element mask. LSB of flattened
mask is expected to correspond to IP instance 0 element index mask.
Currently, HWPM driver incorrectly shifts instance 0 floorsweep mask to
higher bits.
Fix the floorsweep info calculation logic to compute floorsweep mask
correctly.
Use is_ip_active and is_resource_active hals instead of chip specific
functions.
Bug 3737440
Change-Id: I01c1b430cf7fdc2159198770f8b34056dda5ccca
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2754282
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
The device sampler test doesn't consume all PMA records and initiates
device close. This results in PMA engine status to be set to quiesce
state and tegra_hwpm_release() returning with error.
In such case, HWPM driver should close device completely and return any
resultant error.
Closing HWPM device completely ensures that sw state is reset and ready
for next session. And HWPM reset assert during device close resets HWPM
hardware.
Bug 3714516
Change-Id: I9d800bfb7a38f82a295f45a674d14808975a863e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2744657
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
HWPM driver verifies available IP instance elements and updates
corresponding element floorsweep mask in the IP structures. Availability
of the elements is done by reading one perfmux register corresponding to
the element. Since PMA and RTR perfmuxes belong to the HWPM device,
these apertures need to be MMIO mapped to be accessed. Since PMA/RTR
perfmuxes are MMIO mapped at reservation, the availabilty verification
fails to read perfmux registers. This triggers incorrect updates for PMA
element fs mask.
PMA/RTR have pre-defined/pre-initialized element_fs_masks. Hence,
verifying element availabilty for PMA/RTR should be skipped. This change
fixes the issue of PMA marked as invalid.
Bug 3682605
Change-Id: Ib78fde73a1321095315b735b987fe8e2a9aaf474
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2743130
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
There are different clock gating types. Currently, t234 HWPM only
supports SLCG, however it is possible that future chips will include
more CG features.
Rename disable_slcg() and enable_slcg() HALs to disable_cg() and
enable_cg() respectively.
Setting CG features to enabled mode is a PROD value. Hence, call
enable_cg() from init_prod_values().
To make sure that the CG features are disabled during profiling session,
rearrange init_prod_value() function call before disable_cg().
Bug 3682605
Change-Id: I3426603de14a14bce37880a8c47833ae3203665e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2734039
(cherry picked from commit eb5cacc67a551714d453465d4ef070971718375a)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2737531
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
IPs supported for performance management register themselves with
required funtion pointers. The HWPM driver processes the request and
marks the given IP instance valid.
To mark elements of the registered IP instance valid, HWPM reads one of
the allowlist registers. Register read is essential to confirm
availability of the element. Register reads for floorswept elements
should return with error.
Currently, HWPM driver marks all elements of an IP instance as available
at registration time. The process to update element mask considering
floorswept elements is performed during IP reservation.
Users querying floorsweeping info before reservation ioctls would
receive incorrect fs_info masks.
To fix this issue, move updating of IP instance element fs_info at
device open. If device is already opened, update element mask during
registration.
- Implement TEGRA_HWPM_UPDATE_IP_INST_MASK case to update element fs
mask for given IP.
Bug 3685203
Bug 3584061
Change-Id: If992204e6f7debf24b36a94f2b752b5077333cda
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2734732
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Fix following violations reported by sparse tool
- warning: symbol 'tegra_hwpm_debugfs_*' was not declared. Should it
be static?
Add missing header in tegra_hwpm_debugfs.c file to fix this issue
- warning: no newline at end of file
Add new end line in tegra_hwpm_alist_utils.c to fix this issue.
- warning: symbol 't234_chip_info' was not declared. Should it be
static?
Modify t234_chip_info structure to be static to fix this issue.
- warning: symbol '*_perfmon_element_static_array' was not declared.
Should it be static?
- warning: symbol '*_perfmux_element_static_array' was not declared.
Should it be static?
- warning: symbol '*_inst_static_array' was not declared. Should it
be static?
Modify each *_perfmon_element_static_array,
*_perfmux_element_static_array and *_inst_static_array in all IPs to be
static to fix this issue.
Bug 3528414
Change-Id: I58e7a1c6e14988d7315fb8d160aa7f89a2eb4cf5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2725821
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
HWPM is a profiling device. Device node property support-soc-tools
indicates if soc profiling tools should be enabled or disabled.
Add logic to HWPM probe to read device node and probe HWPM device only
if support-soc-tools property is present.
Implement devnode API to disclose device node permissions for HWPM.
Set HWPM device node permissions to allow access for root and group.
Bug 3435136
Bug 3583956
Change-Id: I988de3b21cd00ef9402ca03408d2b0141e7155d8
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2717982
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
GVS: Gerrit_Virtual_Submit
Enum tegra_soc_hwpm_ip is defined to query IP information. To untangle
its use from HWPM related functionality, enum tegra_soc_hwpm_resource
should be used by IP drivers to register with HWPM.
An IP can have multiple instances with multiple IP core elements in
each instance. Currently, the IP <-> HWPM register access API passes
register offset only. However, it is not possible to figure out
requested specific register access only with register offset. For
example, MC device has one instance with 16 duplicate channels. To
access channel x perfmux register, HWPM driver should pass perfmux
register offset alongwith channel number (index).
Add instance element index as an argument to the register access API,
tegra_soc_hwpm_ip_ops.hwpm_ip_reg_op().
-Update internal copy of tegra_soc_hwpm_ip_ops.
-Update hwpm_ip_reg_op() implemented in flcn driver.
-Update hwpm_ip_reg_op() implemented in pva driver.
Update hwpm_ip_pm() in flcn driver to use nvhost power management APIs.
Bug 3573882
Jira THWPM-8
Change-Id: I0138927f383e9a67085816132ce33538bd609560
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2713274
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Currently, read/write functions validate aperture and mmio address
pointers. However, the error cannot be returned to the parent resulting
into undetected errors.
Modify all read write functions to return error on failure. This will
also allow HWPM driver to know about unavailable IP perfmuxes.
Jira THWPM-41
Change-Id: I6cc4ba7a831d5058657d4f2536b1ce3ab20b30c6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2707446
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Introduced macros to define HWPM aperture types perfmon, perfmux and
broadcast.
Added new enum to define element type.
IP perfmux and IP broadcast are handled in similar way. Whereas, HWPM
perfmux should use HWPM perfmon functions.
Updated hwpm structures are as below
Parent HWPM structure
-> Active chip structure
-> Array of IPs
-> HALs
IP structure
-> Array of instances
-> Array of instance info with respect to perfmon, perfmux, broadcast
-> Instance mask : indicates available instances
-> reserved status
Instance structure
-> Array of element info with respect to perfmon, perfmux, broadcast
-> Array of corresponding element structures
-> Element mask : indicates available elements in the instance
Element structure
-> Aperture address details
-> DT node / MMIO details
Update all functions to use new HWPM structures.
Update hwpm_probe to include force IP enable step.
Jira THWPM-41
Change-Id: I9461063d2136b34e841322c4ddd77a20486424c6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2706489
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
PMA and RTR perfmuxes contain registers required to configure HWPM.
So currently, PMA and RTR IPs are treated as special case and
initialized - released along with the driver.
However, as RTR IP includes both router and pma apertures, only treat
RTR as special IP. Change RTR config to have router and pma apertures
as separate instances. Define macros for router and pma instance index.
This will be allow to retrieve router and pma aperture structures.
Remove PMA IP reservation during driver init and PMA IP release at
driver close. As PMA IP is not treated special now,
remove get_pma_ip_idx() HAL.
Modify HWPM configuration functions to use router and pma apertures
initialized as part of RTR IP.
Jira THWPM-41
Change-Id: Ic82b2d07769c1b5c4601e07776be06087468657d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2706488
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
- Many HWPM functions are performed on all apertures of all instances of
all IPs. Define below resource utility functions to perform a task on
all IPs, instances and apertures:
- tegra_hwpm_func_all_IPs
- tegra_hwpm_func_single_ip
- tegra_hwpm_func_all_instance
- tegra_hwpm_func_single_instance
- tegra_hwpm_func_all_perfmuxes
- tegra_hwpm_func_all_perfmons
- tegra_hwpm_func_single_aperture
- Modify below functions to use above mentioned utility functions:
- get allowlist size
- combine allowlist
- reserve resources
- bind resources
- release resources
This will make code more legible and maintainable.
This patch also defines new function that validates all HAL
initializations for the chip.
Jira THWPM-41
Change-Id: Icaeba4d94187b97022c0a6626584e7d61ab6d0e4
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2705524
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Add below HALs to make code chip agnostic. This will allow us to use
t234 specific HALs for next chips.
- get_pma_int_idx: get PMA's internal index corresponding to active chip
- get_rtr_int_idx: get RTR's internal index corresponding to active chip
- get_ip_max_idx: get MAX IP index corresponding to active chip
Move chip agnostic code to common files.
Jira THWPM-41
Change-Id: I5518469b1473fe7f66b6517cee729cf46520bbac
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2675515
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
HWPM supports various IPs which initialize at different times in boot
flow. Some IPs such as MSS, NVLINK initialize before HWPM device and
some IPs (VIC, OFA, NVDEC, NVDLA) are initialized after HWPM device.
Modify IP register function to store registration requests in a
linked list for IPs initialized before HWPM device is probed.
The linked list will be traversed to complete pending IP register
requests after HWPM device is initialized.
- Add struct tegra_hwpm_ip_ops internal to HWPM driver to include only
required ip_ops details.
- Replace init_fs_info HAL with finalize_chip_info to register ip_ops,
force enable IPs (if any).
Jira THWPM-41
Change-Id: I916b4fa50679e79025a941a9c1fc113bdfe92b41
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2675472
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Set the floorsweeping information for IPs only
if the configuration is non Hypervisor. Force
enable IPs are only valid for native-Linux config.
On hypervisor config, a driver is allowed to only
remap addresses owned by the device node.
Thus, ioremap of perfmux addresses is not allowed
in hypervisor configuration. Add check to prevent
force enable IPs and ioremap in hypervisor
configuration.
JIRA THWPM-45
Change-Id: I8fe6d3c4984c66be5a117e0cc2164ea20a5374cb
Signed-off-by: vasukis <vasukis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2674003
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
For MSS channel, hwpm client expects floorsweep info mask to indicate
available MSS chanenel perfmuxes.
HWPM driver would prefer to follow common fs_mask logic for IPs and is
being discussed.
Temporarily update floorsweep info logic for MSS channel, until
floorsweep info IOCTL modifications are finalized.
Bug 3477617
Change-Id: I75b51ccc60151e801dec50fa32b15b951db6e47e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2672291
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
- Update HWPM driver to add HAL layer. This will allow support for multiple chips.
- Add below data structure hierarchy for HWPM driver
HWPM driver structure -> chip info struct -> ip info array -> perfmux/perfmon info array
NOTE: To make commit message more legible, using "aperture" instead of "perfmux and/or perfmon"
- Chip info structure contains
- Array of IP info
- HAL function pointers
- IP info structure contains IP specific info
- Number of instances
- Number of apertures per instance
- Aperture ranges, strides, static info array
- Aperture dynamic arrays
- Aperture info structure contains
- Hw index
- Physical address info
- MMIO address info
- Add separate IP info files
- Create separate files that include logic for allowlist, memory buffer, resources, ip, regops to make functions more legible.
- Move probe, ioctl and io functions to os/linux path.
- Add fn, info, register and verbose debug log levels to controls debug messages
- add debugfs node to update dbg_mask
- Correct MGBE perfmux base address
Jira THWPM-41
Change-Id: I8ffdaa657789e2a187cbb98502d0359bb57f9c54
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2651377
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Move chip specific code to chip specific folder. This will allow
multiple chip support in the future.
Create new specific functions
- Initialize hwpm structures
- Reserve and release PMA and RTR apertures
- Zero, update and check allowlists
- Set and get fake registers for MC aperture on simulation
- perfmon dt aperture enums
Jira THWPM-41
Change-Id: Ib80f324283c8d29b5c6f7bb6345a6df2410954e6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2620234
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
