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memory: tegra: Update allowlist of PERFMUX registers

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Add few PERFMUX register offsets to allowlist for SOC-HWPM to access.

Bug 4704678

Change-Id: Ica7c6d2a7fc47699abf0969eef1b4b4a518a5b78
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3221623
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Ashish Mhetre
2024-10-01 04:47:17 +00:00
committed by Jon Hunter
parent 6d78ed22c7
commit 01b31bbabb
1 changed files with 5 additions and 1 deletions
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6
drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c
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@@ -18,6 +18,9 @@
#define MC_MCC_CTL_PERFMUX_OFFSET 0x8914
#define MC_MCC_DP_PERFMUX_OFFSET 0x8918
#define MC_CBRIDGE_PERFMUX_OFFSET 0x891c
#define MSS_HUB_IB_PERFMUX_OFFSET 0x6f3c
#define MSS_HUB_CIF_PERFMUX_OFFSET 0x6f34
#define MSS_HUB_TU_PERFMUX_0 0x6f38
#define MAX_MC_CHANNELS 17 // Broadcast Channel + 16 MC Channels
@@ -66,7 +69,8 @@ static int tegra_mc_hwpm_reg_op(void *ip_dev,
}
if (reg_offset != MC_MCC_CTL_PERFMUX_OFFSET && reg_offset != MC_MCC_DP_PERFMUX_OFFSET &&
reg_offset != MC_CBRIDGE_PERFMUX_OFFSET) {
reg_offset != MC_CBRIDGE_PERFMUX_OFFSET && reg_offset != MSS_HUB_IB_PERFMUX_OFFSET &&
reg_offset != MSS_HUB_CIF_PERFMUX_OFFSET && reg_offset != MSS_HUB_TU_PERFMUX_0) {
dev_err(dev, "SOC-HWPM requesting access to prohibited register");
return -EPERM;
}