mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-24 02:01:36 +03:00
arm64: Remove Tegra194 device-tree
Tegra194 is no longer supported and all testing has now been disabled,
so remove the Tegra194 device-tree.
Bug 4047365
Change-Id: Id6b65f6761652785e04cc850fd4b4ef6ed8cc20e
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3017348
(cherry picked from commit e7020ca405)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3029977
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Jon Hunter
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@@ -1,41 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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# Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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objtree = $(srctree)
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# Redefine the fixdep command
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cmd_and_fixdep = \
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$(cmd); \
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$(objtree)/scripts/basic/fixdep $(depfile) $@ '$(make-cmd)' > $(dot-target).cmd;\
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rm -f $(depfile)
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include $(oottree)/scripts/Makefile.lib
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oot-dtstree = $(oottree)/arch/arm64/boot/dts/nvidia
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DTB_LIST := $(dtb-y)
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DTBO_LIST := $(dtbo-y)
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dtb-y :=
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dts_makefile=$(foreach d,$(wildcard $1*), $(call dts_makefile,$(d)/,$(2)) $(if $(findstring Makefile,$(d)),$(d)))
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dts_mfiles = $(call dts_makefile, $(oot-dtstree), Makefile)
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ifneq ($(dts_mfiles),)
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dts-include :=
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include $(dts_mfiles)
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dtb-y := $(addprefix nvidia/,$(dtb-y))
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dtbo-y := $(addprefix nvidia/,$(dtbo-y))
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endif
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DTC_INCLUDE := $(oottree)/include
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DTB_LIST += $(dtb-y)
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DTBO_LIST += $(dtbo-y)
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DTB_OBJS := $(addprefix $(obj)/,$(DTB_LIST))
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DTBO_OBJS := $(addprefix $(obj)/,$(DTBO_LIST))
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dtbs: $(DTB_OBJS) $(DTBO_OBJS) FORCE
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dtbsclean:
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find $(oot-dtstree) -name *.dtb | xargs rm -rf
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find $(oot-dtstree) -name *.dtbo | xargs rm -rf
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find $(oot-dtstree) -name *.tmp | xargs rm -rf
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@@ -1,9 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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# Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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DTC_FLAGS += -@
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# DT overlays
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dtbo-y += tegra194-carveouts.dtbo
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dtbo-y += tegra194-jetson.dtbo
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dtbo-y += tegra194-p3509-0000+p3668-0001-overlay.dtbo
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@@ -1,29 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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/plugin/;
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/ {
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fragment@0 {
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target-path = "/";
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__overlay__ {
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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vpr: vpr-carveout {
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compatible = "nvidia,vpr-carveout";
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status = "okay";
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};
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};
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tegra-carveouts {
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compatible = "nvidia,carveouts-t19x";
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memory-region = <&vpr>;
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status = "okay";
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};
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};
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};
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};
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@@ -1,157 +0,0 @@
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/*
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* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/clock/tegra194-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/memory/tegra194-mc.h>
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#include <dt-bindings/power/tegra194-powergate.h>
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#include <dt-bindings/reset/tegra194-reset.h>
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/ {
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overlay-name = "Tegra194 Jetson Overlay";
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compatible = "nvidia,tegra194";
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fragment@0 {
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target-path = "/bus@0/host1x@13e00000";
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__overlay__ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>,
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<0x0 0x24f00000 0x0 0x24f00000 0x0 0x00100000>;
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nvdla0@15880000 {
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compatible = "nvidia,tegra194-nvdla";
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reg = <0x0 0x15880000 0x0 0x00040000>;
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interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_DLA0_CORE>,
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<&bpmp TEGRA194_CLK_DLA0_FALCON>;
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clock-names = "nvdla", "nvdla_flcn";
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resets = <&bpmp TEGRA194_RESET_DLA0>;
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reset-names = "nvdla";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DLAA>;
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_DLA0RDA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA0FALRDB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA0WRA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA0FALWRB &emc>;
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interconnect-names = "dma-mem", "read-1", "write", "write-1";
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iommus = <&smmu TEGRA194_SID_NVDLA0>;
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dma-coherent;
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};
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nvdla1@158c0000 {
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compatible = "nvidia,tegra194-nvdla";
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reg = <0x0 0x158c0000 0x0 0x00040000>;
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interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_DLA1_CORE>,
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<&bpmp TEGRA194_CLK_DLA1_FALCON>;
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clock-names = "nvdla", "nvdla_flcn";
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resets = <&bpmp TEGRA194_RESET_DLA1>;
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reset-names = "nvdla";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DLAB>;
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_DLA1RDA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA1FALRDB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA1WRA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_DLA1FALWRB &emc>;
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interconnect-names = "dma-mem", "read-1", "write", "write-1";
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iommus = <&smmu TEGRA194_SID_NVDLA1>;
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dma-coherent;
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};
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pva0@16000000 {
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compatible = "nvidia,tegra194-pva";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PVAA>;
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reg = <0x0 0x16000000 0x0 0x00800000>,
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<0x0 0x24f00000 0x0 0x00080000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&bpmp TEGRA194_RESET_PVA0_ALL>;
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reset-names = "nvpva";
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clocks = <&bpmp TEGRA194_CLK_NAFLL_PVA_VPS>,
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<&bpmp TEGRA194_CLK_NAFLL_PVA_CORE>,
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<&bpmp TEGRA194_CLK_PVA0_AXI>,
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<&bpmp TEGRA194_CLK_PVA0_VPS0>,
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<&bpmp TEGRA194_CLK_PVA0_VPS1>;
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clock-names = "nafll_pva_vps", "nafll_pva_core", "axi", "vps0", "vps1";
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_PVA0RDA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA0RDB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA0RDC &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA0WRA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA0WRB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA0WRC &emc>;
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interconnect-names = "dma-mem", "read-b", "read-c", "write-a", "write-b", "write-c";
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iommus = <&smmu TEGRA194_SID_PVA0>;
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dma-coherent;
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};
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pva1@16800000 {
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compatible = "nvidia,tegra194-pva";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PVAB>;
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reg = <0x0 0x16800000 0x0 0x00800000>,
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<0x0 0x24f80000 0x0 0x00080000>;
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interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&bpmp TEGRA194_RESET_PVA1_ALL>;
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reset-names = "nvpva";
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clocks = <&bpmp TEGRA194_CLK_PVA1_AXI>,
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<&bpmp TEGRA194_CLK_PVA1_VPS0>,
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<&bpmp TEGRA194_CLK_PVA1_VPS1>;
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clock-names = "axi", "vps0", "vps1";
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_PVA1RDA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA1RDB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA1RDC &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA1WRA &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA1WRB &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_PVA1WRC &emc>;
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interconnect-names = "dma-mem", "read-b", "read-c", "write-a", "write-b", "write-c";
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iommus = <&smmu TEGRA194_SID_PVA1>;
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dma-coherent;
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};
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};
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};
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fragment@1 {
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target-path = "/";
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__overlay__ {
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#address-cells = <2>;
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#size-cells = <2>;
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cvnas@14000000 {
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compatible = "nvidia,tegra194-cvnas";
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reg = <0x0 0x14000000 0x0 0x20000>, /* CV0_REG0_BASE */
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<0x0 0x14020000 0x0 0x10000>, /* CV0_SRAM_BASE */
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<0x0 0x0b240000 0x0 0x10000>; /* HSM_BASE */
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_CVNAS>;
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assigned-clocks = <&bpmp TEGRA194_CLK_CVNAS>;
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assigned-clock-rates = <1356800000>;
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resets = <&bpmp TEGRA194_RESET_CVNAS>,
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<&bpmp TEGRA194_RESET_CVNAS_FCM>;
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reset-names = "rst", "rst_fcm";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_CV>;
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cvsramslice = <4 0x1000>;
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cvsram-reg = <0x0 0x50000000 0x0 0x400000>;
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};
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};
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};
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};
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@@ -1,9 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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/plugin/;
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/ {
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overlay-name = "Add p3509-0000+p3668-0001 Overlay Support";
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compatible = "nvidia,tegra194";
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};
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