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ASoC: tegra-alt: audio fixes

Browse Source 
fixes for:
a) asrc
b) arad
c) machine driver

List of CL's:
http://git-master/r/799350
http://git-master/r/799941
http://git-master/r/801101

Bug 200133225

Change-Id: Icbec3b988e134c47dc13cbf64bbef394bc31b0a6
Signed-off-by: Dipesh Gandhi <dipeshg@nvidia.com>
Reviewed-on: http://git-master/r/823283
Reviewed-by: Sharad Gupta <sharadg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Pai <npai@nvidia.com>
This commit is contained in:
Dipesh Gandhi
2015-10-27 12:16:31 +05:30
committed by Sameer Pujar
parent eb7dacf7ea
commit 34b3cc18d3
2 changed files with 19 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
sound/soc/tegra-alt/tegra186_arad_alt.c
View File

@@ -808,12 +808,16 @@ static int tegra186_arad_platform_probe(struct platform_device *pdev)
ret = -ENODEV;
goto err;
}
tegra186_arad_runtime_resume(&pdev->dev);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = tegra186_arad_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
ret = snd_soc_register_codec(&pdev->dev, &tegra186_arad_codec,
tegra186_arad_dais,
ARRAY_SIZE(tegra186_arad_dais));
if (ret != 0) {
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
goto err_suspend;
}
#ifdef CONFIG_SND_SOC_TEGRA186_ARAD_WAR
@@ -826,14 +830,6 @@ static int tegra186_arad_platform_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "Could not register ARAD INTERRUPT\n");
spin_lock_init(&arad->int_lock);
#endif
ret = snd_soc_register_codec(&pdev->dev, &tegra186_arad_codec,
tegra186_arad_dais,
ARRAY_SIZE(tegra186_arad_dais));
if (ret != 0) {
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
goto err_suspend;
}
return 0;
err_suspend:

23
sound/soc/tegra-alt/tegra186_asrc_alt.c
View File

@@ -209,6 +209,8 @@ static int tegra186_asrc_runtime_resume(struct device *dev)
regcache_cache_only(asrc->regmap, false);
regcache_sync(asrc->regmap);
regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_INT_CLEAR,
0x01);
for (lane_id = 0; lane_id < 6; lane_id++) {
if (asrc->lane[lane_id].ratio_source == RATIO_SW) {
regmap_write(asrc->regmap,
@@ -619,37 +621,37 @@ static const struct snd_kcontrol_new tegra186_asrc_controls[] = {
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT("Ratio1 Frac", TEGRA186_ASRC_STREAM1_RATIO_FRAC_PART,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MAX, 0,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT("Ratio2 Int", TEGRA186_ASRC_STREAM2_RATIO_INTEGER_PART,
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT("Ratio2 Frac", TEGRA186_ASRC_STREAM2_RATIO_FRAC_PART,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MAX, 0,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT("Ratio3 Int", TEGRA186_ASRC_STREAM3_RATIO_INTEGER_PART,
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT("Ratio3 Frac", TEGRA186_ASRC_STREAM3_RATIO_FRAC_PART,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MAX, 0,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT("Ratio4 Int", TEGRA186_ASRC_STREAM4_RATIO_INTEGER_PART,
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT("Ratio4 Frac", TEGRA186_ASRC_STREAM4_RATIO_FRAC_PART,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MAX, 0,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT("Ratio5 Int", TEGRA186_ASRC_STREAM5_RATIO_INTEGER_PART,
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT("Ratio5 Frac", TEGRA186_ASRC_STREAM5_RATIO_FRAC_PART,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MAX, 0,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_SINGLE_EXT("Ratio6 Int", TEGRA186_ASRC_STREAM6_RATIO_INTEGER_PART,
0, TEGRA186_ASRC_STREAM_RATIO_INTEGER_PART_MASK, 0,
tegra186_asrc_get_ratio_int, tegra186_asrc_put_ratio_int),
SOC_SINGLE_EXT("Ratio6 Frac", TEGRA186_ASRC_STREAM6_RATIO_FRAC_PART,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK, 0,
0, TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MAX, 0,
tegra186_asrc_get_ratio_frac, tegra186_asrc_put_ratio_frac),
SOC_ENUM_EXT("Ratio1 SRC", src_select1,
@@ -945,11 +947,7 @@ static int tegra186_asrc_platform_probe(struct platform_device *pdev)
}
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = tegra186_asrc_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
tegra186_asrc_runtime_resume(&pdev->dev);
regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_CONFIG,
TEGRA186_ASRC_GLOBAL_CONFIG_FRAC_32BIT_PRECISION);
@@ -959,10 +957,11 @@ static int tegra186_asrc_platform_probe(struct platform_device *pdev)
TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR,
ASRC_ARAM_START_ADDR);
regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_INT_MASK,
0x01);
/* set global enable */
regmap_write(asrc->regmap,
TEGRA186_ASRC_GLOBAL_ENB, TEGRA186_ASRC_GLOBAL_EN);
/* initialize default output srate */
for (i = 0; i < 6; i++) {
asrc->lane[i].int_part = 1;