tegra-cec: Fix cec_irq flooding issue

The RX_REGISTER_FULL interrupt is not cleared when rx_fifo_data is 0.
Add readw for RX_REGISTER when rx_fifo_data is 0 so that the interrupt
can be cleared.

Bug 5266075

Change-Id: I10ab107efadc22a6ec79255e22bf080384b4ff5c
Signed-off-by: Robert Huang <robhuang@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3367190
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Prafull Suryawanshi <prafulls@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
This commit is contained in:
Robert Huang
2025-05-20 07:03:17 +00:00
committed by Jon Hunter
parent cfb3723972
commit 38578736f2

View File

@@ -343,6 +343,11 @@ static irqreturn_t tegra_cec_irq_handler(int irq, void *data)
readw(cec->cec_base + TEGRA_CEC_RX_REGISTER);
}
if (cec->rx_fifo_data == 0) {
dev_info(dev, "rx_fifo_data is empty.\n");
readw(cec->cec_base + TEGRA_CEC_RX_REGISTER);
}
tegra_cec_writel(TEGRA_CEC_INT_STAT_RX_REGISTER_FULL,
cec->cec_base + TEGRA_CEC_INT_STAT);