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platform: tegra: dce: add dce kernel driver
For T23x, we have a separate R5 based cluster named as Display Controller Engine(DCE) to run our Display RM code. This driver will run on CPU with the following functionality: Via debugfs for test and bring-up purposes: 1. Reads the DCE firmware image into DRAM. 2. Sets up DCE AST to cover the DCE firmware image. 3. Sets up R5 reset vector to point to DCE firmware entry point 4. Brings DCE out of reset 5. Dumps various regsiters for debug In production env: 1. Manages interrupts to CPU from DCE 2. Uses bootstrap command interface to define Admin IPC 3. Locks down bootstrap command interface 4. Uses Admin IPC to define message IPC 5. Uses Admin IPC to define message IPC payload area 6. Uses Admin IPC to set IPC channels 6. Uses Admin IPC to define crashdump area (optional) 7. Provides IPC interfaces for any DCE Client running on CCPLEX including Display RM. 8. Uses Admin IPC to set logging level (optional) This patch puts a framework in place with the following features : 1. Firmware Loading 2. AST Configuration 3. DCE Reset with EVP Programming 4. Logging Infra 5. Debugfs Support 6. Interrupt Handling 7. Mailbox Programming 8. IPC Programming 9. DCE Client Interface 10. Ftrace Support for debug purposes Change-Id: Idd28cd9254706c7313f531fcadaa7024a5b344e7 Signed-off-by: Arun Swain <arswain@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2289865 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-by: Santosh Galma <galmar@nvidia.com> Reviewed-by: Mitch Luban <mluban@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Mahesh Kumar <mahkumar@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Arun Swain
committed by
Laxman Dewangan
Laxman Dewangan
parent
fe2085dcef
commit
606f03fbf2
156
drivers/platform/tegra/dce/include/interface/dce-admin-cmds.h
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156
drivers/platform/tegra/dce/include/interface/dce-admin-cmds.h
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@@ -0,0 +1,156 @@
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/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* NVIDIA Corporation and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA Corporation is strictly prohibited.
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*/
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#ifndef DCE_ADMIN_CMDS_H
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#define DCE_ADMIN_CMDS_H
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#include <interface/dce-types.h>
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/*
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* Version of the ADMIN command interface.
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*
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* This MUST be updated any time any changes are made to the ADMIN
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* commands.
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*
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* To keep things simple, this value should be incremented by 1 each
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* time changes are made.
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*/
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#define DCE_ADMIN_VERSION 2
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#define DCE_ADMIN_CMD_SIZE sizeof(struct dce_admin_ipc_cmd)
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#define DCE_ADMIN_RESP_SIZE sizeof(struct dce_admin_ipc_resp)
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#define DCE_ADMIN_CMD_CHAN_FSIZE max(DCE_ADMIN_CMD_SIZE, \
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DCE_ADMIN_RESP_SIZE)
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#define DCE_ADMIN_CMD_MAX_NFRAMES 4
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#define DCE_ADMIN_CMD_VERSION 0x00U // returns version of interface
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#define DCE_ADMIN_CMD_HOST_VERSION 0x01U // host supplied version
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#define DCE_ADMIN_CMD_GET_FW_VERSION 0x02U // return FW version info
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#define DCE_ADMIN_CMD_ECHO 0x02U // echo data back to CCPLEX
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#define DCE_ADMIN_CMD_MEM_MAP 0x03U // map a region of memory
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#define DCE_ADMIN_CMD_MEM_INFO 0x04U // return info about a region
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#define DCE_ADMIN_CMD_IPC_INFO 0x05U // return IPC chan info
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#define DCE_ADMIN_CMD_IPC_CREATE 0x06U // create an IPC channel
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#define DCE_ADMIN_CMD_PREPARE_SC7 0x07U // prepare to enter SC7
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#define DCE_ADMIN_CMD_ENTER_SC7 0x08U // enter SC7
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#define DCE_ADMIN_CMD_SET_LOGGING 0x09U // set logging level
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#define DCE_ADMIN_CMD_GET_LOG_INFO 0x08U // get current log info
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#define DCE_ADMIN_CMD_LOCK_CHANGES 0x0AU // lock creating new channels
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// and changing memory areas
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#define DCE_ADMIN_CMD_CODE_COVERAGE_START 0x0BU // start collecting code
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// coverage data
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#define DCE_ADMIN_CMD_CODE_COVERAGE_STOP 0x0CU // stop collecting code
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// coverage data
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#define DCE_ADMIN_CMD_PERF_START 0x0DU // start collecting perf data
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#define DCE_ADMIN_CMD_PERF_STOP 0x0EU // stop collecting perf data
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#define DCE_ADMIN_CMD_TEST_START 0x0FU // start tests
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#define DCE_ADMIN_CMD_TEST_STOP 0x10U // stop tests and return status
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#define DCE_ADMIN_CMD_DEBUG 0x11U // debug command
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#define DCE_ADMIN_CMD_RM_BOOTSTRAP 0x12U // tell RM to "bootstrap"
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#define DCE_ADMIN_CMD_NEXT 0x13U // must be last command ID + 1
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struct dce_admin_version_info {
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uint32_t version;
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};
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struct dce_admin_fw_version_info {
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uint32_t bootstrap_interface;
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uint32_t admin_interface;
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uint32_t driver_headers;
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uint32_t core_interface;
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uint8_t fw_version[4];
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uint32_t gcid_revision;
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uint8_t safertos_major;
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uint8_t safertos_minor;
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};
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struct dce_admin_echo {
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uint32_t data;
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};
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struct dce_admin_log_args {
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uint32_t log_enable;
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uint32_t log_level;
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};
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struct dce_admin_mem_args {
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uint32_t region;
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dce_iova iova;
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uint32_t length;
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uint32_t sid;
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};
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struct dce_admin_ipc_info_args {
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uint32_t type;
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};
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struct dce_admin_ipc_signal {
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uint32_t signal_type;
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union {
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uint32_t mailbox;
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struct {
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uint32_t doorbell_num;
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uint32_t doorbell_bit_num;
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} doorbell;
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} signal;
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uint32_t semaphore;
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uint32_t semaphore_bit_num;
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};
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struct dce_admin_ipc_info {
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uint32_t type;
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uint32_t flags;
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uint32_t mem_region;
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dce_iova rd_iova;
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dce_iova wr_iova;
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uint32_t fsize;
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uint32_t n_frames;
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struct dce_admin_ipc_signal signal_from_dce;
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struct dce_admin_ipc_signal signal_to_dce;
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};
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struct dce_admin_ipc_create_args {
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uint32_t type;
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dce_iova rd_iova;
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dce_iova wr_iova;
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uint32_t fsize;
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uint32_t n_frames;
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};
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struct dce_admin_ipc_cmd {
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uint32_t cmd;
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union {
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struct dce_admin_version_info version;
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struct dce_admin_echo echo;
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struct dce_admin_log_args log;
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struct dce_admin_ipc_info_args ipc_info;
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struct dce_admin_mem_args mem_map;
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struct dce_admin_ipc_create_args ipc_create;
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} args;
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};
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struct dce_admin_ipc_resp {
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uint32_t error;
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union {
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struct dce_admin_version_info version;
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struct dce_admin_echo echo;
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struct dce_admin_log_args log;
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struct dce_admin_ipc_info ipc;
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struct dce_admin_mem_args mem_info;
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struct dce_admin_fw_version_info fw_version;
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} args;
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};
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#endif
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27
drivers/platform/tegra/dce/include/interface/dce-bitops.h
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27
drivers/platform/tegra/dce/include/interface/dce-bitops.h
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@@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* NVIDIA Corporation and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA Corporation is strictly prohibited.
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*/
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#ifndef DCE_BITOPS_H
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#define DCE_BITOPS_H
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#define DCE_BIT(_b_) (((uint32_t)1U) << (_b_))
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#define DCE_MASK(_msb_, _lsb_) \
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(((DCE_BIT(_msb_) - (uint32_t)1U) | \
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DCE_BIT(_msb_)) & (~(DCE_BIT(_lsb_) - (uint32_t)1U)))
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#define DCE_EXTRACT(_x_, _msb_, _lsb_, _type_) \
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((_type_)((_type_)((_x_) & DCE_MASK(_msb_, _lsb_)) >> (_lsb_)))
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#define DCE_INSERT(_x_, _msb_, _lsb_, _value_) \
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((((uint32_t)_x_) & DCE_MASK(_msb_, _lsb_)) | \
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((((uint32_t)_value_) << _lsb_) & DCE_MASK(_msb_, _lsb_)))
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#endif
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111
drivers/platform/tegra/dce/include/interface/dce-boot-cmds.h
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111
drivers/platform/tegra/dce/include/interface/dce-boot-cmds.h
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@@ -0,0 +1,111 @@
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/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* NVIDIA Corporation and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA Corporation is strictly prohibited.
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*/
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#ifndef DCE_BOOT_CMDS_H
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#define DCE_BOOT_CMDS_H
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#include <interface/dce-bitops.h>
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/*
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* Version of the bootstrap command interface.
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*
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* This MUST be updated any time any changes are made to the
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* bootstrap commands.
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*
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* To keep things simple, this value should be incremented by 1
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* each time changes are made.
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*/
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#define DCE_BOOT_CMD_VERSION_NUM 2
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/*
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* Defines the various bootstrap commands to DCE.
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*
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* These commands are relatively simple and are mainly used to
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* communicate with DCE during initialization.
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*
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* The fundamental layout of a command is:
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* Bit(s) Field Description
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* 31:31 GO Signals to the DCE that a command is to be
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* processed
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* 30:27 COMMAND Identifies the command that the DCE is to
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* process
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* 26 RESERVED should be 0
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* 25 HILO 0 = PARM is 19:0 of address
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* 1 = PARM is 39:20 of address
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* 24 RDWR 0 = read header
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* 1 = write header
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* 23:20 RESERVED should be 0
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* 19:0 PARM Parameter to the command
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*
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* Once the command has been processed and the CCPLEX receives an interrupt
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* from DCE, the mailbox used will contain any information about the result
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* of the command.
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*
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* The commands are:
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*
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* DCE_BOOT_CMD_VERSION returns the version of the interface
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* DCE_BOOT_CMD_SET_SID sets the SID for a buffer
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* DCE_BOOT_CMD_CHANNEL_INIT initialize an IVC channel
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* DCE_BOOT_CMD_SET_ADDR set the channel address
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* DCE_BOOT_CMD_GET_FSIZE get the size of the frame
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* DCE_BOOT_CMD_SET_NFRAMES set the number of frames
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* DCE_BOOT_CMD_RESET causes DCE to reset to its initial state.
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* This does not cause DCE to reboot. It mearly
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* indicates that all of memory buffers for IPC
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* will be ignored and the CCPLEX will have to
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* re-establish the memory again.
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*
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* DCE_BOOT_CMD_LOCK locks the admin command interface. Requires
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* a full reset of DCE to unlock.
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*/
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#define DCE_BOOT_CMD_GO DCE_BIT(31)
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#define DCE_BOOT_CMD_SET(_x_, _v_) DCE_INSERT(_x_, 30, 27, _v_)
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#define DCE_BOOT_CMD_GET(_x_) DCE_EXTRACT(_x_, 30, 27, uint32_t)
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#define DCE_BOOT_CMD_SET_HILO(_x_, _v_) DCE_INSERT(_x_, 25, 25, _v_)
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#define DCE_BOOT_CMD_GET_HILO(_x_) DCE_EXTRACT(_x_, 25, 25, uint32_t)
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#define DCE_BOOT_CMD_SET_RDWR(_x_, _v_) DCE_INSERT(_x_, 24, 24, _v_)
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#define DCE_BOOT_CMD_GET_RDWR(_x_) DCE_EXTRACT(_x_, 24, 24, uint32_t)
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#define DCE_BOOT_CMD_PARM_SET(_x_, _v_) DCE_INSERT(_x_, 19, 0, _v_)
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#define DCE_BOOT_CMD_PARM_GET(_x_) DCE_EXTRACT(_x_, 19, 0, uint32_t)
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/*
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* Commands
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*/
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#define DCE_BOOT_CMD_VERSION (0x00U)
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#define DCE_BOOT_CMD_SET_SID (0x01U)
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#define DCE_BOOT_CMD_CHANNEL_INIT (0x02U)
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#define DCE_BOOT_CMD_SET_ADDR (0x03U)
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#define DCE_BOOT_CMD_GET_FSIZE (0x04U)
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#define DCE_BOOT_CMD_SET_NFRAMES (0x05U)
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#define DCE_BOOT_CMD_RESET (0x06U)
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#define DCE_BOOT_CMD_LOCK (0x07U)
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#define DCE_BOOT_CMD_SET_AST_LENGTH (0x08U)
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#define DCE_BOOT_CMD_SET_AST_IOVA (0x09U)
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#define DCE_BOOT_CMD_SET_FSIZE (0x0AU)
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#define DCE_BOOT_CMD_UNUSED_11 (0x0BU)
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#define DCE_BOOT_CMD_UNUSED_12 (0x0CU)
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#define DCE_BOOT_CMD_UNUSED_13 (0x0DU)
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#define DCE_BOOT_CMD_UNUSED_14 (0x0EU)
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#define DCE_BOOT_CMD_UNUSED_15 (0x0FU)
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#define DCE_BOOT_CMD_NEXT (0x10U)
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/*
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* Boot Command Errors
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*/
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#define DCE_BOOT_CMD_ERR_FLAG DCE_BIT(23)
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#define DCE_BOOT_CMD_NO_ERROR 0U
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#define DCE_BOOT_CMD_ERR_BAD_COMMAND (1U | DCE_BOOT_CMD_ERR_FLAG)
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#define DCE_BOOT_CMD_ERR_UNIMPLEMENTED (2U | DCE_BOOT_CMD_ERR_FLAG)
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#define DCE_BOOT_CMD_ERR_IPC_SETUP (3U | DCE_BOOT_CMD_ERR_FLAG)
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#define DCE_BOOT_CMD_ERR_INVALID_NFRAMES (4U | DCE_BOOT_CMD_ERR_FLAG)
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#define DCE_BOOT_CMD_ERR_IPC_CREATE (5U | DCE_BOOT_CMD_ERR_FLAG)
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#define DCE_BOOT_CMD_ERR_LOCKED (6U | DCE_BOOT_CMD_ERR_FLAG)
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#endif
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@@ -0,0 +1,34 @@
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/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
|
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*
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* NVIDIA Corporation and its licensors retain all intellectual property
|
||||
* and proprietary rights in and to this software, related documentation
|
||||
* and any modifications thereto. Any use, reproduction, disclosure or
|
||||
* distribution of this software and related documentation without an express
|
||||
* license agreement from NVIDIA Corporation is strictly prohibited.
|
||||
*/
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#ifndef DCE_CORE_INTERFACE_IPC_TYPES_H
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#define DCE_CORE_INTERFACE_IPC_TYPES_H
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/*
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* Because this file is to be shared between DCE Core, RM and driver,
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* it must not include or reference anything that is not contained
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* in the following header files:
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* stdint.h
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* stddef.h
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* stdbool.h
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*/
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typedef uint32_t dce_ipc_type_t;
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#define DCE_IPC_TYPE_ADMIN ((dce_ipc_type_t)0U)
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#define DCE_IPC_TYPE_DISPRM ((dce_ipc_type_t)1U)
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#define DCE_IPC_TYPE_HDCP ((dce_ipc_type_t)2U)
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#define DCE_IPC_TYPE_RM_NOTIFY ((dce_ipc_type_t)3U)
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#define DCE_IPC_TYPE_BPMP ((dce_ipc_type_t)4U)
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#define DCE_IPC_TYPE_MAX ((dce_ipc_type_t)5U)
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#endif
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@@ -0,0 +1,25 @@
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/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* NVIDIA Corporation and its licensors retain all intellectual property
|
||||
* and proprietary rights in and to this software, related documentation
|
||||
* and any modifications thereto. Any use, reproduction, disclosure or
|
||||
* distribution of this software and related documentation without an express
|
||||
* license agreement from NVIDIA Corporation is strictly prohibited.
|
||||
*/
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#ifndef DCE_DRIVER_HEADER_VERSION_H
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#define DCE_DRIVER_HEADER_VERSION_H
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/*
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* Version of the headers shared between the driver and DCE FW.
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*
|
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* This MUST be updated any time any changes are made to the headers
|
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* that are shared between the driver and DCE FW.
|
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*
|
||||
* To keep things simple, this value should be incremented by 1 each
|
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* time changes are made.
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*/
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#define DCE_DRIVER_HEADER_VERSION 2
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#endif
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112
drivers/platform/tegra/dce/include/interface/dce-interface.h
Normal file
112
drivers/platform/tegra/dce/include/interface/dce-interface.h
Normal file
@@ -0,0 +1,112 @@
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/*
|
||||
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* NVIDIA Corporation and its licensors retain all intellectual property
|
||||
* and proprietary rights in and to this software, related documentation
|
||||
* and any modifications thereto. Any use, reproduction, disclosure or
|
||||
* distribution of this software and related documentation without an express
|
||||
* license agreement from NVIDIA Corporation is strictly prohibited.
|
||||
*/
|
||||
|
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#ifndef DCE_INTERFACE_H
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#define DCE_INTERFACE_H
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#include <interface/dce-bitops.h>
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/*
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* XXX: TODO
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*
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* These should be defined in terms of the HW registers
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*/
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#define DCE_NUM_SEMA_REGS 4
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#define DCE_NUM_MBOX_REGS 8
|
||||
|
||||
/*
|
||||
* Symbolic definitions of the semaphore registers
|
||||
*/
|
||||
typedef uint32_t hsp_sema_t;
|
||||
|
||||
#define DCE_BOOT_SEMA (hsp_sema_t)0U
|
||||
|
||||
/*
|
||||
* Definitions for DCE_BOOT_SEMA
|
||||
*
|
||||
* Used to communicate bits of information between the OS and DCE
|
||||
*/
|
||||
|
||||
/*
|
||||
* Bits set by the OS and examined by the R5
|
||||
*/
|
||||
#define DCE_BOOT_INT DCE_BIT(31) // interrupt when DCE is ready
|
||||
#define DCE_WAIT_DEBUG DCE_BIT(30) // wait in debug loop
|
||||
#define DCE_SC7_RESUME DCE_BIT(29) // resume using saved SC7 state
|
||||
// rather than a full restart
|
||||
|
||||
/*
|
||||
* Bits set by the R5 and examined by the OS
|
||||
*/
|
||||
#define DCE_BOOT_TCM_COPY DCE_BIT(15) // uCode has copied to TCM
|
||||
#define DCE_BOOT_HW_INIT DCE_BIT(14) // hardware init complete
|
||||
#define DCE_BOOT_MPU_INIT DCE_BIT(13) // MPU initialized
|
||||
#define DCE_BOOT_CACHE_INIT DCE_BIT(12) // cache initialized
|
||||
#define DCE_BOOT_R5_INIT DCE_BIT(11) // R5 initialized
|
||||
#define DCE_BOOT_DRIVER_INIT DCE_BIT(10) // driver init complete
|
||||
#define DCE_BOOT_MAIN_STARTED DCE_BIT(9) // main started
|
||||
#define DCE_BOOT_TASK_INIT_START DCE_BIT(8) // task initialization started
|
||||
#define DCE_BOOT_TASK_INIT_DONE DCE_BIT(7) // task initialization complete
|
||||
|
||||
#define DCE_HALTED DCE_BIT(1) // uCode has halted
|
||||
#define DCE_BOOT_COMPLETE DCE_BIT(0) // uCode boot has completed
|
||||
|
||||
/*
|
||||
* Symbolic definitions of the doorbell registers
|
||||
*/
|
||||
typedef uint32_t hsp_db_t;
|
||||
|
||||
/*
|
||||
* Symbolic definitions of the mailbox registers (rather than using 0-7)
|
||||
*/
|
||||
typedef uint32_t hsp_mbox_t;
|
||||
|
||||
#define DCE_MBOX_FROM_DCE_RM (hsp_mbox_t)0U // signal from RM IPC
|
||||
#define DCE_MBOX_TO_DCE_RM (hsp_mbox_t)1U // signal to RM IPC
|
||||
#define DCE_MBOX_FROM_BPMP (hsp_mbox_t)2U // signal from BPMP IPC
|
||||
#define DCE_MBOX_TO_BPMP (hsp_mbox_t)3U // signal to BPMP IPC
|
||||
#define DCE_MBOX_FROM_DCE_ADMIN (hsp_mbox_t)4U // signal from DCE ADMIN IPC
|
||||
#define DCE_MBOX_TO_DCE_ADMIN (hsp_mbox_t)5U // signal to ADMIN IPC
|
||||
#define DCE_MBOX_BOOT_CMD (hsp_mbox_t)6U // boot commands
|
||||
#define DCE_MBOX_IRQ (hsp_mbox_t)7U // general interrupt/status
|
||||
/*
|
||||
* Generic interrupts & status from the DCE are reported in DCE_MBOX_IRQ
|
||||
*/
|
||||
#define DCE_IRQ_PENDING DCE_BIT(31)// interrupt is pending
|
||||
|
||||
#define DCE_IRQ_GET_STATUS_TYPE(_x_) DCE_EXTRACT(_x_, 30, 27, uint32_t)
|
||||
#define DCE_IRQ_SET_STATUS_TYPE(_x_) DCE_INSERT(0U, 30, 27, _x_)
|
||||
|
||||
#define DCE_IRQ_STATUS_TYPE_IRQ 0x0 // irq status
|
||||
#define DCE_IRQ_STATUS_TYPE_BOOT_CMD 0x1 // boot command status
|
||||
|
||||
#define NUM_DCE_IRQ_STATUS_TYPES 2
|
||||
|
||||
#define DCE_IRQ_GET_STATUS(_x_) DCE_EXTRACT(_x_, 23, 0, uint32_t)
|
||||
#define DCE_IRQ_SET_STATUS(_x_) DCE_INSERT(0U, 23, 0, _x_)
|
||||
|
||||
/*
|
||||
* Bits in status field when IRQ_STATUS_TYPE == IRQ_STATUS_TYPE_IRQ
|
||||
*/
|
||||
#define DCE_IRQ_READY DCE_BIT(23) // DCE is ready
|
||||
#define DCE_IRQ_LOG_OVERFLOW DCE_BIT(22) // trace log overflow
|
||||
#define DCE_IRQ_LOG_READY DCE_BIT(21) // trace log buffers available
|
||||
#define DCE_IRQ_CRASH_LOG DCE_BIT(20) // crash log available
|
||||
#define DCE_IRQ_ABORT DCE_BIT(19) // uCode abort occurred
|
||||
#define DCE_IRQ_SC7_ENTERED DCE_BIT(18) // DCE state saved
|
||||
// can be powered off
|
||||
|
||||
/*
|
||||
* MBOX contents for IPC are the same for all of the mailboxes that are
|
||||
* used for signaling IPC. Not all values will be useful for all mailboxes.
|
||||
*/
|
||||
#define DCE_IPC_IRQ_PENDING DCE_BIT(31) // interrupt is pending
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* NVIDIA Corporation and its licensors retain all intellectual property
|
||||
* and proprietary rights in and to this software, related documentation
|
||||
* and any modifications thereto. Any use, reproduction, disclosure or
|
||||
* distribution of this software and related documentation without an express
|
||||
* license agreement from NVIDIA Corporation is strictly prohibited.
|
||||
*/
|
||||
|
||||
#ifndef DCE_IPC_HEADER_H
|
||||
#define DCE_IPC_HEADER_H
|
||||
|
||||
struct dce_ipc_header {
|
||||
uint32_t length;
|
||||
};
|
||||
|
||||
#endif
|
||||
36
drivers/platform/tegra/dce/include/interface/dce-ipc-state.h
Normal file
36
drivers/platform/tegra/dce/include/interface/dce-ipc-state.h
Normal file
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* NVIDIA Corporation and its licensors retain all intellectual property
|
||||
* and proprietary rights in and to this software, related documentation
|
||||
* and any modifications thereto. Any use, reproduction, disclosure or
|
||||
* distribution of this software and related documentation without an express
|
||||
* license agreement from NVIDIA Corporation is strictly prohibited.
|
||||
*/
|
||||
|
||||
#ifndef DCE_IPC_STATE_H
|
||||
#define DCE_IPC_STATE_H
|
||||
|
||||
#include <interface/dce-bitops.h>
|
||||
|
||||
/*
|
||||
* Flags used to denote the state of IPC data structures
|
||||
*/
|
||||
typedef uint32_t dce_ipc_flags_t;
|
||||
|
||||
#define DCE_IPC_FL_VALID ((dce_ipc_flags_t)DCE_BIT(0))
|
||||
#define DCE_IPC_FL_REGISTERED ((dce_ipc_flags_t)DCE_BIT(1))
|
||||
#define DCE_IPC_FL_INIT ((dce_ipc_flags_t)DCE_BIT(2))
|
||||
#define DCE_IPC_FL_READY ((dce_ipc_flags_t)DCE_BIT(3))
|
||||
#define DCE_IPC_FL_RM_ALLOWED ((dce_ipc_flags_t)DCE_BIT(4))
|
||||
#define DCE_IPC_FL_MSG_HEADER ((dce_ipc_flags_t)DCE_BIT(15))
|
||||
|
||||
/*
|
||||
* Different types of signal mechanisms
|
||||
*/
|
||||
typedef uint32_t dce_ipc_signal_type_t;
|
||||
|
||||
#define DCE_IPC_SIGNAL_MAILBOX ((dce_ipc_signal_type_t)0U)
|
||||
#define DCE_IPC_SIGNAL_DOORBELL ((dce_ipc_signal_type_t)1U)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* NVIDIA Corporation and its licensors retain all intellectual property
|
||||
* and proprietary rights in and to this software, related documentation
|
||||
* and any modifications thereto. Any use, reproduction, disclosure or
|
||||
* distribution of this software and related documentation without an express
|
||||
* license agreement from NVIDIA Corporation is strictly prohibited.
|
||||
*/
|
||||
|
||||
#ifndef DCE_MEMORY_IDS_H
|
||||
#define DCE_MEMORY_IDS_H
|
||||
|
||||
/*
|
||||
* Defines the varous memory IDs used for mapping memory regions
|
||||
* for DCE.
|
||||
*
|
||||
* XXX: TODO
|
||||
* Rename some of the IDs to better represent what they're used for
|
||||
*/
|
||||
|
||||
#define DCE_MAP_DRAM_ID 0U // FW DRAM
|
||||
#define DCE_MAP_BPMP_ID 1U // BPMP communications area
|
||||
#define DCE_MAP_CONFIG_DATA_ID 2U // device tree
|
||||
#define DCE_MAP_IPC_ID 3U // memory region for IPC
|
||||
#define DCE_MAP_MSG_ID 4U // extra: rename at some point
|
||||
#define DCE_MAP_UTILITY_ID 5U // extra: rename at some point
|
||||
#define DCE_MAP_RM_ID 6U // RM communications area
|
||||
#define DCE_MAP_RM_DATA_ID 7U // extra RM data area
|
||||
|
||||
#endif
|
||||
16
drivers/platform/tegra/dce/include/interface/dce-types.h
Normal file
16
drivers/platform/tegra/dce/include/interface/dce-types.h
Normal file
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* NVIDIA Corporation and its licensors retain all intellectual property
|
||||
* and proprietary rights in and to this software, related documentation
|
||||
* and any modifications thereto. Any use, reproduction, disclosure or
|
||||
* distribution of this software and related documentation without an express
|
||||
* license agreement from NVIDIA Corporation is strictly prohibited.
|
||||
*/
|
||||
|
||||
#ifndef DCE_TYPES_H
|
||||
#define DCE_TYPES_H
|
||||
|
||||
typedef uint64_t dce_iova;
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user