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ASoC: tegra: update AHUB drivers as per upstream

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AHUB and few components have been pushed for upstream review. Though the
changes are still under review, we can leverage the work done on upstream
5.x and use the same here on 5.4 kernel. This helps to align the downstream
code. Any changes that happen because of upstream review can be cherry
picked here. If we plan for any downstream changes, upstream patch needs to
be pushed to keep the code in sync.

As of today current snapshot is pulled from v3 of AHUB series,
http://patchwork.ozlabs.org/project/linux-tegra/list/?series=159664

Above series was worked on later versions of linux-next and hence following
are the changes required for porting back on 5.4
 * tegra_pcm_new() and tegra_pcm_free() are exposed from tegra_pcm.c and
   component driver callbacks use these.
 * Callback functions required for snd_pcm_ops in component driver are
   implemented by tegra_pcm.c
 * With this ADMAIF driver need not register platform device with ASoC
   core.

For components (AHUB, ADMAIF, I2S, DMIC and DSPK) the downsream code
differs in few aspects from the code that was pushed for v3. Some of them
are listed below.
 * I2S driver in downstream implements startup()/shutdown() calls for DAI,
   which does some setup related to pinconfig and regulators. The same is
   true for DMIC and DSPK drivers as well.
 * Downstream ADMAIF drivers makes bandwidth requests in startup/shutdown()
   calls and has helper function for dumping registers. It also has
   additional DAI interfaces which are used for ADSP audio.
 * Downstream AHUB driver has DAI interfaces for connecting to all other
   modules.
These differences will be cherry-picked as and when it is necessary.

Bug 2845498

Change-Id: Id374967ecae26f6b7334a959fb23308d383c15f2
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
This commit is contained in:
Sameer Pujar
2020-02-24 11:48:08 +05:30
parent 39e4507117
commit 6b98f0a740
10 changed files with 2198 additions and 2421 deletions
Download Patch File Download Diff File Expand all files Collapse all files

590
sound/soc/tegra/tegra186_dspk.c
View File

@@ -1,88 +1,86 @@
// SPDX-License-Identifier: GPL-2.0-only
/* /*
* tegra186_dspk_alt.c - Tegra186 DSPK driver * tegra186_dspk.c - Tegra186 DSPK driver
* *
* Copyright (c) 2015-2019 NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/device.h> #include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <sound/core.h> #include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h> #include <sound/pcm_params.h>
#include <sound/soc.h> #include <sound/soc.h>
#include <linux/of_device.h> #include "tegra186_dspk.h"
#include <soc/tegra/chip-id.h> #include "tegra_cif.h"
#include <linux/pinctrl/pinconf-tegra.h>
#include "tegra210_xbar_alt.h"
#include "tegra186_dspk_alt.h"
#include "ahub_unit_fpga_clock.h"
#define DRV_NAME "tegra186-dspk"
static const struct reg_default tegra186_dspk_reg_defaults[] = { static const struct reg_default tegra186_dspk_reg_defaults[] = {
{ TEGRA186_DSPK_AXBAR_RX_INT_MASK, 0x00000007}, { TEGRA186_DSPK_RX_INT_MASK, 0x00000007 },
{ TEGRA186_DSPK_AXBAR_RX_CIF_CTRL, 0x00007700}, { TEGRA186_DSPK_RX_CIF_CTRL, 0x00007700 },
{ TEGRA186_DSPK_CG, 0x00000001}, { TEGRA186_DSPK_CG, 0x00000001 },
{ TEGRA186_DSPK_CORE_CTRL, 0x00000310}, { TEGRA186_DSPK_CORE_CTRL, 0x00000310 },
{ TEGRA186_DSPK_CODEC_CTRL, 0x03000000}, { TEGRA186_DSPK_CODEC_CTRL, 0x03000000 },
{ TEGRA186_DSPK_SDM_COEF_A_2, 0x000013bb},
{ TEGRA186_DSPK_SDM_COEF_A_3, 0x00001cbf},
{ TEGRA186_DSPK_SDM_COEF_A_4, 0x000029d7},
{ TEGRA186_DSPK_SDM_COEF_A_5, 0x00003782},
{ TEGRA186_DSPK_SDM_COEF_C_1, 0x000000a6},
{ TEGRA186_DSPK_SDM_COEF_C_2, 0x00001959},
{ TEGRA186_DSPK_SDM_COEF_C_3, 0x00002b9f},
{ TEGRA186_DSPK_SDM_COEF_C_4, 0x00004218},
{ TEGRA186_DSPK_SDM_COEF_G_1, 0x00000074},
{ TEGRA186_DSPK_SDM_COEF_G_2, 0x0000007d},
}; };
static int tegra186_dspk_get_control(struct snd_kcontrol *kcontrol, static int tegra186_dspk_get_control(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol) struct snd_ctl_elem_value *ucontrol)
{ {
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_codec_get_drvdata(codec); struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
if (strstr(kcontrol->id.name, "Rx fifo threshold")) if (strstr(kcontrol->id.name, "FIFO Threshold"))
ucontrol->value.integer.value[0] = dspk->rx_fifo_th; ucontrol->value.integer.value[0] = dspk->rx_fifo_th;
else if (strstr(kcontrol->id.name, "OSR Value")) else if (strstr(kcontrol->id.name, "OSR Value"))
ucontrol->value.integer.value[0] = dspk->osr_val; ucontrol->value.integer.value[0] = dspk->osr_val;
else if (strstr(kcontrol->id.name, "LR Polarity Select"))
ucontrol->value.integer.value[0] = dspk->lrsel;
else if (strstr(kcontrol->id.name, "Sample Rate"))
ucontrol->value.integer.value[0] = dspk->srate_override;
else if (strstr(kcontrol->id.name, "Audio Channels"))
ucontrol->value.integer.value[0] = dspk->audio_ch_override;
else if (strstr(kcontrol->id.name, "Channel Select"))
ucontrol->value.integer.value[0] = dspk->ch_sel;
else if (strstr(kcontrol->id.name, "Audio Bit Format"))
ucontrol->value.integer.value[0] = dspk->audio_fmt_override;
else if (strstr(kcontrol->id.name, "Mono To Stereo"))
ucontrol->value.integer.value[0] = dspk->mono_to_stereo;
else if (strstr(kcontrol->id.name, "Stereo To Mono"))
ucontrol->value.integer.value[0] = dspk->stereo_to_mono;
return 0; return 0;
} }
static int tegra186_dspk_put_control(struct snd_kcontrol *kcontrol, static int tegra186_dspk_put_control(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol) struct snd_ctl_elem_value *ucontrol)
{ {
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); struct snd_soc_component *codec = snd_soc_kcontrol_component(kcontrol);
struct tegra186_dspk *dspk = snd_soc_codec_get_drvdata(codec); struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
int val = ucontrol->value.integer.value[0]; int val = ucontrol->value.integer.value[0];
if (strstr(kcontrol->id.name, "Rx fifo threshold")) { if (strstr(kcontrol->id.name, "FIFO Threshold"))
if (val >= 0 && val < TEGRA186_DSPK_RX_FIFO_DEPTH) dspk->rx_fifo_th = val;
dspk->rx_fifo_th = val; else if (strstr(kcontrol->id.name, "OSR Value"))
else
return -EINVAL;
} else if (strstr(kcontrol->id.name, "OSR Value"))
dspk->osr_val = val; dspk->osr_val = val;
else if (strstr(kcontrol->id.name, "LR Polarity Select"))
dspk->lrsel = val;
else if (strstr(kcontrol->id.name, "Sample Rate"))
dspk->srate_override = val;
else if (strstr(kcontrol->id.name, "Audio Channels"))
dspk->audio_ch_override = val;
else if (strstr(kcontrol->id.name, "Channel Select"))
dspk->ch_sel = val;
else if (strstr(kcontrol->id.name, "Audio Bit Format"))
dspk->audio_fmt_override = val;
else if (strstr(kcontrol->id.name, "Mono To Stereo"))
dspk->mono_to_stereo = val;
else if (strstr(kcontrol->id.name, "Stereo To Mono"))
dspk->stereo_to_mono = val;
return 0; return 0;
} }
@@ -94,8 +92,7 @@ static int tegra186_dspk_runtime_suspend(struct device *dev)
regcache_cache_only(dspk->regmap, true); regcache_cache_only(dspk->regmap, true);
regcache_mark_dirty(dspk->regmap); regcache_mark_dirty(dspk->regmap);
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) clk_disable_unprepare(dspk->clk_dspk);
clk_disable_unprepare(dspk->clk_dspk);
return 0; return 0;
} }
@@ -103,14 +100,12 @@ static int tegra186_dspk_runtime_suspend(struct device *dev)
static int tegra186_dspk_runtime_resume(struct device *dev) static int tegra186_dspk_runtime_resume(struct device *dev)
{ {
struct tegra186_dspk *dspk = dev_get_drvdata(dev); struct tegra186_dspk *dspk = dev_get_drvdata(dev);
int ret; int err;
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) { err = clk_prepare_enable(dspk->clk_dspk);
ret = clk_prepare_enable(dspk->clk_dspk); if (err) {
if (ret) { dev_err(dev, "failed to enable DSPK clock, err: %d\n", err);
dev_err(dev, "clk_enable failed: %d\n", ret); return err;
return ret;
}
} }
regcache_cache_only(dspk->regmap, false); regcache_cache_only(dspk->regmap, false);
@@ -119,114 +114,129 @@ static int tegra186_dspk_runtime_resume(struct device *dev)
return 0; return 0;
} }
static int tegra186_dspk_set_audio_cif(struct tegra186_dspk *dspk, static const unsigned int tegra186_dspk_fmts[] = {
struct snd_pcm_hw_params *params, 0,
unsigned int reg, struct snd_soc_dai *dai) TEGRA_ACIF_BITS_16,
TEGRA_ACIF_BITS_32,
};
static int tegra186_dspk_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{ {
int channels, max_th; struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);
struct tegra210_xbar_cif_conf cif_conf; unsigned int channels, srate, dspk_clk;
struct device *dev = dai->dev; struct device *dev = dai->dev;
struct tegra_cif_conf cif_conf;
unsigned int max_th;
int err;
memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
channels = params_channels(params); channels = params_channels(params);
memset(&cif_conf, 0, sizeof(struct tegra210_xbar_cif_conf)); cif_conf.audio_ch = channels;
cif_conf.audio_channels = channels;
cif_conf.client_channels = channels;
cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_24;
/* RX FIFO threshold interms of frames */ /* Override audio channel */
max_th = (TEGRA186_DSPK_RX_FIFO_DEPTH / channels) - 1; if (dspk->audio_ch_override)
max_th = (max_th < 0) ? 0 : max_th; cif_conf.audio_ch = dspk->audio_ch_override;
if (dspk->rx_fifo_th > max_th) { /* error handling */
cif_conf.threshold = max_th;
dspk->rx_fifo_th = max_th;
} else
cif_conf.threshold = dspk->rx_fifo_th;
switch (params_format(params)) { /* Client channel */
case SNDRV_PCM_FORMAT_S16_LE: switch (dspk->ch_sel) {
cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_16; case DSPK_CH_SELECT_LEFT:
cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_16; case DSPK_CH_SELECT_RIGHT:
cif_conf.client_ch = 1;
break; break;
case SNDRV_PCM_FORMAT_S32_LE: case DSPK_CH_SELECT_STEREO:
cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_32; cif_conf.client_ch = 2;
break; break;
default: default:
dev_err(dev, "Wrong format!\n"); dev_err(dev, "Invalid DSPK client channels\n");
return -EINVAL; return -EINVAL;
} }
tegra210_xbar_set_cif(dspk->regmap, TEGRA186_DSPK_AXBAR_RX_CIF_CTRL, cif_conf.client_bits = TEGRA_ACIF_BITS_24;
&cif_conf);
return 0;
}
static int tegra186_dspk_startup(struct snd_pcm_substream *substream, switch (params_format(params)) {
struct snd_soc_dai *dai) case SNDRV_PCM_FORMAT_S16_LE:
{ cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
struct device *dev = dai->dev; cif_conf.client_bits = TEGRA_ACIF_BITS_16;
struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai); break;
int ret; case SNDRV_PCM_FORMAT_S32_LE:
cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
if (dspk->prod_name != NULL) { break;
ret = tegra_pinctrl_config_prod(dev, dspk->prod_name); default:
if (ret < 0) dev_err(dev, "unsupported format!\n");
dev_warn(dev, "Failed to set %s setting\n", return -ENOTSUPP;
dspk->prod_name);
} }
return 0; /* Audio bit format override */
} if (dspk->audio_fmt_override)
cif_conf.audio_bits =
tegra186_dspk_fmts[dspk->audio_fmt_override];
static int tegra186_dspk_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);
int channels, srate, ret, dspk_clk;
int osr = dspk->osr_val;
int interface_clk_ratio = 4; /* dspk interface clock should be fsout*4 */
channels = params_channels(params);
srate = params_rate(params); srate = params_rate(params);
dspk_clk = (1 << (5+osr)) * srate * interface_clk_ratio; /* Sample rate override */
if (dspk->srate_override)
srate = dspk->srate_override;
if ((tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) { /* RX FIFO threshold in terms of frames */
program_dspk_clk(dspk_clk); max_th = (TEGRA186_DSPK_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1;
} else {
ret = clk_set_rate(dspk->clk_dspk, dspk_clk); if (dspk->rx_fifo_th > max_th)
if (ret) { dspk->rx_fifo_th = max_th;
dev_err(dev, "Can't set dspk clock rate: %d\n", ret);
return ret; cif_conf.threshold = dspk->rx_fifo_th;
} cif_conf.mono_conv = dspk->mono_to_stereo;
cif_conf.stereo_conv = dspk->stereo_to_mono;
tegra_set_cif(dspk->regmap, TEGRA186_DSPK_RX_CIF_CTRL,
&cif_conf);
/*
* DSPK clock and PDM codec clock should be synchronous with 4:1 ratio,
* this is because it takes 4 clock cycles to send out one sample to
* codec by sigma delta modulator. Finally the clock rate is a multiple
* of 'Over Sampling Ratio', 'Sample Rate' and 'Interface Clock Ratio'.
*/
dspk_clk = (DSPK_OSR_FACTOR << dspk->osr_val) * srate * DSPK_CLK_RATIO;
err = clk_set_rate(dspk->clk_dspk, dspk_clk);
if (err) {
dev_err(dev, "can't set DSPK clock rate %u, err: %d\n",
dspk_clk, err);
return err;
} }
regmap_update_bits(dspk->regmap, regmap_update_bits(dspk->regmap,
TEGRA186_DSPK_CORE_CTRL, /* Reg */
TEGRA186_DSPK_OSR_MASK, TEGRA186_DSPK_CORE_CTRL,
osr << TEGRA186_DSPK_OSR_SHIFT); /* Mask */
TEGRA186_DSPK_OSR_MASK |
TEGRA186_DSPK_CHANNEL_SELECT_MASK |
TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK,
/* Value */
(dspk->osr_val << DSPK_OSR_SHIFT) |
((dspk->ch_sel + 1) << CH_SEL_SHIFT) |
(dspk->lrsel << LRSEL_POL_SHIFT));
regmap_update_bits(dspk->regmap, return 0;
TEGRA186_DSPK_CORE_CTRL,
TEGRA186_DSPK_CHANNEL_SELECT_MASK,
((1 << channels) - 1) <<
TEGRA186_DSPK_CHANNEL_SELECT_SHIFT);
/* program cif control register */
ret = tegra186_dspk_set_audio_cif(dspk, params,
TEGRA186_DSPK_AXBAR_RX_CIF_CTRL,
dai);
if (ret)
dev_err(dev, "Can't set dspk RX CIF: %d\n", ret);
return ret;
} }
static struct snd_soc_dai_ops tegra186_dspk_dai_ops = { static const struct snd_soc_dai_ops tegra186_dspk_dai_ops = {
.hw_params = tegra186_dspk_hw_params, .hw_params = tegra186_dspk_hw_params,
.startup = tegra186_dspk_startup,
}; };
/*
* Three DAIs are exposed
* 1. "CIF" DAI for connecting with XBAR
* 2. "DAP" DAI for connecting with CODEC
* 3. "DUMMY_SINK" can be used when no external
* codec connection is available. In such case
* "DAP" is connected with "DUMMY_SINK"
* Order of these DAIs should not be changed, since DAI links in DT refer
* to these DAIs depending on the index.
*/
static struct snd_soc_dai_driver tegra186_dspk_dais[] = { static struct snd_soc_dai_driver tegra186_dspk_dais[] = {
{ {
.name = "CIF", .name = "CIF",
@@ -252,33 +262,6 @@ static struct snd_soc_dai_driver tegra186_dspk_dais[] = {
.ops = &tegra186_dspk_dai_ops, .ops = &tegra186_dspk_dai_ops,
.symmetric_rates = 1, .symmetric_rates = 1,
}, },
/* The second DAI is used when the output of the DSPK is connected
* to two mono codecs. When the output of the DSPK is connected to
* a single stereo codec, then only the first DAI should be used.
*/
{
.name = "CIF2",
.playback = {
.stream_name = "CIF2 Receive",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
},
{
.name = "DAP2",
.capture = {
.stream_name = "DAP2 Transmit",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
},
.symmetric_rates = 1,
},
{ {
.name = "DUMMY_SINK", .name = "DUMMY_SINK",
.playback = { .playback = {
@@ -294,74 +277,107 @@ static struct snd_soc_dai_driver tegra186_dspk_dais[] = {
static const struct snd_soc_dapm_widget tegra186_dspk_widgets[] = { static const struct snd_soc_dapm_widget tegra186_dspk_widgets[] = {
SND_SOC_DAPM_AIF_OUT("DAP TX", NULL, 0, TEGRA186_DSPK_ENABLE, 0, 0), SND_SOC_DAPM_AIF_OUT("DAP TX", NULL, 0, TEGRA186_DSPK_ENABLE, 0, 0),
SND_SOC_DAPM_AIF_OUT("DAP2 TX", NULL, 0, 0, 0, 0),
SND_SOC_DAPM_SPK("Dummy Output", NULL), SND_SOC_DAPM_SPK("Dummy Output", NULL),
}; };
static const struct snd_soc_dapm_route tegra186_dspk_routes[] = { static const struct snd_soc_dapm_route tegra186_dspk_routes[] = {
{ "DAP TX", NULL, "CIF Receive" }, { "DAP TX", NULL, "CIF Receive" },
{ "DAP Transmit", NULL, "DAP TX" }, { "DAP Transmit", NULL, "DAP TX" },
{ "DAP2 TX", NULL, "CIF2 Receive" }, { "Dummy Output", NULL, "Dummy Playback" },
{ "DAP2 Transmit", NULL, "DAP2 TX" },
{ "Dummy Output", NULL, "Dummy Playback" },
}; };
static const char * const tegra186_dspk_format_text[] = {
"None",
"16",
"32",
};
static const struct soc_enum tegra186_dspk_format_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_format_text),
tegra186_dspk_format_text);
static const char * const tegra186_dspk_ch_sel_text[] = {
"Left", "Right", "Stereo",
};
static const struct soc_enum tegra186_dspk_ch_sel_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_ch_sel_text),
tegra186_dspk_ch_sel_text);
static const char * const tegra186_dspk_osr_text[] = { static const char * const tegra186_dspk_osr_text[] = {
"OSR_32", "OSR_64", "OSR_128", "OSR_256", "OSR_32", "OSR_64", "OSR_128", "OSR_256",
}; };
static const struct soc_enum tegra186_dspk_osr_enum = static const struct soc_enum tegra186_dspk_osr_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_osr_text),
ARRAY_SIZE(tegra186_dspk_osr_text), tegra186_dspk_osr_text);
tegra186_dspk_osr_text);
#define NV_SOC_SINGLE_RANGE_EXT(xname, xmin, xmax, xget, xput) \ static const char * const tegra186_dspk_lrsel_text[] = {
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ "Left", "Right",
.info = snd_soc_info_xr_sx, .get = xget, .put = xput, \ };
.private_value = (unsigned long)&(struct soc_mixer_control) \
{.invert = 0, .min = xmin, .max = xmax, \ static const char * const tegra186_dspk_mono_conv_text[] = {
.platform_max = xmax} \ "ZERO", "COPY",
} };
static const struct soc_enum tegra186_dspk_mono_conv_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(tegra186_dspk_mono_conv_text),
tegra186_dspk_mono_conv_text);
static const char * const tegra186_dspk_stereo_conv_text[] = {
"CH0", "CH1", "AVG",
};
static const struct soc_enum tegra186_dspk_stereo_conv_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
ARRAY_SIZE(tegra186_dspk_stereo_conv_text),
tegra186_dspk_stereo_conv_text);
static const struct soc_enum tegra186_dspk_lrsel_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra186_dspk_lrsel_text),
tegra186_dspk_lrsel_text);
static const struct snd_kcontrol_new tegrat186_dspk_controls[] = { static const struct snd_kcontrol_new tegrat186_dspk_controls[] = {
NV_SOC_SINGLE_RANGE_EXT("Rx fifo threshold", 0, SOC_SINGLE_EXT("FIFO Threshold", SND_SOC_NOPM, 0,
TEGRA186_DSPK_RX_FIFO_DEPTH - 1, tegra186_dspk_get_control, TEGRA186_DSPK_RX_FIFO_DEPTH - 1, 0,
tegra186_dspk_put_control), tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("OSR Value", tegra186_dspk_osr_enum, SOC_ENUM_EXT("OSR Value", tegra186_dspk_osr_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control), tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("LR Polarity Select", tegra186_dspk_lrsel_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_SINGLE_EXT("Sample Rate", SND_SOC_NOPM, 0, 48000, 0,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_SINGLE_EXT("Audio Channels", SND_SOC_NOPM, 0, 2, 0,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("Channel Select", tegra186_dspk_ch_sel_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("Audio Bit Format", tegra186_dspk_format_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("Mono To Stereo", tegra186_dspk_mono_conv_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control),
SOC_ENUM_EXT("Stereo To Mono", tegra186_dspk_stereo_conv_enum,
tegra186_dspk_get_control, tegra186_dspk_put_control),
}; };
static struct snd_soc_codec_driver tegra186_dspk_codec = { static const struct snd_soc_component_driver tegra186_dspk_cmpnt = {
.idle_bias_off = 1, .dapm_widgets = tegra186_dspk_widgets,
.component_driver = { .num_dapm_widgets = ARRAY_SIZE(tegra186_dspk_widgets),
.dapm_widgets = tegra186_dspk_widgets, .dapm_routes = tegra186_dspk_routes,
.num_dapm_widgets = ARRAY_SIZE(tegra186_dspk_widgets), .num_dapm_routes = ARRAY_SIZE(tegra186_dspk_routes),
.dapm_routes = tegra186_dspk_routes, .controls = tegrat186_dspk_controls,
.num_dapm_routes = ARRAY_SIZE(tegra186_dspk_routes), .num_controls = ARRAY_SIZE(tegrat186_dspk_controls),
.controls = tegrat186_dspk_controls,
.num_controls = ARRAY_SIZE(tegrat186_dspk_controls),
},
}; };
/* Regmap callback functions */
static bool tegra186_dspk_wr_reg(struct device *dev, unsigned int reg) static bool tegra186_dspk_wr_reg(struct device *dev, unsigned int reg)
{ {
switch (reg) { switch (reg) {
case TEGRA186_DSPK_AXBAR_RX_INT_MASK: case TEGRA186_DSPK_RX_INT_MASK ... TEGRA186_DSPK_RX_CIF_CTRL:
case TEGRA186_DSPK_AXBAR_RX_INT_SET: case TEGRA186_DSPK_ENABLE ... TEGRA186_DSPK_CG:
case TEGRA186_DSPK_AXBAR_RX_INT_CLEAR: case TEGRA186_DSPK_CORE_CTRL ... TEGRA186_DSPK_CODEC_CTRL:
case TEGRA186_DSPK_AXBAR_RX_CIF_CTRL:
case TEGRA186_DSPK_AXBAR_RX_CYA:
case TEGRA186_DSPK_ENABLE:
case TEGRA186_DSPK_SOFT_RESET:
case TEGRA186_DSPK_CG:
return true; return true;
default: default:
if (((reg % 4) == 0) && (reg >= TEGRA186_DSPK_CORE_CTRL) && return false;
(reg <= TEGRA186_DSPK_SDM_COEF_G_2))
return true;
else
return false;
}; };
} }
@@ -371,27 +387,8 @@ static bool tegra186_dspk_rd_reg(struct device *dev, unsigned int reg)
return true; return true;
switch (reg) { switch (reg) {
case TEGRA186_DSPK_AXBAR_RX_STATUS: case TEGRA186_DSPK_RX_STATUS:
case TEGRA186_DSPK_AXBAR_RX_INT_STATUS: case TEGRA186_DSPK_RX_INT_STATUS:
case TEGRA186_DSPK_AXBAR_RX_CIF_FIFO_STATUS:
case TEGRA186_DSPK_STATUS:
case TEGRA186_DSPK_INT_STATUS:
return true;
default:
if (((reg % 4) == 0) && (reg >= TEGRA186_DSPK_DEBUG_STATUS) &&
(reg <= TEGRA186_DSPK_DEBUG_STAGE4_CNTR))
return true;
else
return false;
};
}
static bool tegra186_dspk_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case TEGRA186_DSPK_AXBAR_RX_STATUS:
case TEGRA186_DSPK_AXBAR_RX_INT_STATUS:
case TEGRA186_DSPK_AXBAR_RX_CIF_FIFO_STATUS:
case TEGRA186_DSPK_STATUS: case TEGRA186_DSPK_STATUS:
case TEGRA186_DSPK_INT_STATUS: case TEGRA186_DSPK_INT_STATUS:
return true; return true;
@@ -400,114 +397,105 @@ static bool tegra186_dspk_volatile_reg(struct device *dev, unsigned int reg)
}; };
} }
static const struct regmap_config tegra186_dspk_regmap_config = { static bool tegra186_dspk_volatile_reg(struct device *dev, unsigned int reg)
.reg_bits = 32, {
.reg_stride = 4, switch (reg) {
.val_bits = 32, case TEGRA186_DSPK_RX_STATUS:
.max_register = TEGRA186_DSPK_DEBUG_STAGE4_CNTR, case TEGRA186_DSPK_RX_INT_STATUS:
.writeable_reg = tegra186_dspk_wr_reg, case TEGRA186_DSPK_STATUS:
.readable_reg = tegra186_dspk_rd_reg, case TEGRA186_DSPK_INT_STATUS:
.volatile_reg = tegra186_dspk_volatile_reg, return true;
.precious_reg = NULL, default:
.reg_defaults = tegra186_dspk_reg_defaults, return false;
.num_reg_defaults = ARRAY_SIZE(tegra186_dspk_reg_defaults), };
.cache_type = REGCACHE_FLAT, }
static const struct regmap_config tegra186_dspk_regmap = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = TEGRA186_DSPK_CODEC_CTRL,
.writeable_reg = tegra186_dspk_wr_reg,
.readable_reg = tegra186_dspk_rd_reg,
.volatile_reg = tegra186_dspk_volatile_reg,
.reg_defaults = tegra186_dspk_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra186_dspk_reg_defaults),
.cache_type = REGCACHE_FLAT,
}; };
static const struct of_device_id tegra186_dspk_of_match[] = { static const struct of_device_id tegra186_dspk_of_match[] = {
{ .compatible = "nvidia,tegra186-dspk" }, { .compatible = "nvidia,tegra186-dspk" },
{}, {},
}; };
MODULE_DEVICE_TABLE(of, tegra186_dspk_of_match);
static int tegra186_dspk_platform_probe(struct platform_device *pdev) static int tegra186_dspk_platform_probe(struct platform_device *pdev)
{ {
struct device *dev = &pdev->dev;
struct tegra186_dspk *dspk; struct tegra186_dspk *dspk;
struct device_node *np = pdev->dev.of_node;
struct resource *mem;
void __iomem *regs; void __iomem *regs;
int ret = 0; int err;
const struct of_device_id *match;
match = of_match_device(tegra186_dspk_of_match, &pdev->dev); dspk = devm_kzalloc(dev, sizeof(*dspk), GFP_KERNEL);
if (!match) {
dev_err(&pdev->dev, "Error: No device match found\n");
return -ENODEV;
}
dspk = devm_kzalloc(&pdev->dev, sizeof(*dspk), GFP_KERNEL);
if (!dspk) if (!dspk)
return -ENOMEM; return -ENOMEM;
dspk->prod_name = NULL; dspk->osr_val = DSPK_OSR_64;
dspk->rx_fifo_th = 0; dspk->lrsel = DSPK_LRSEL_LEFT;
dspk->osr_val = TEGRA186_DSPK_OSR_64; dspk->ch_sel = DSPK_CH_SELECT_STEREO;
dev_set_drvdata(&pdev->dev, dspk); dspk->mono_to_stereo = 0; /* "ZERO" */
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) { dev_set_drvdata(dev, dspk);
dspk->clk_dspk = devm_clk_get(&pdev->dev, "dspk");
if (IS_ERR(dspk->clk_dspk)) { dspk->clk_dspk = devm_clk_get(dev, "dspk");
dev_err(&pdev->dev, "Can't retrieve dspk clock\n"); if (IS_ERR(dspk->clk_dspk)) {
return PTR_ERR(dspk->clk_dspk); dev_err(dev, "can't retrieve DSPK clock\n");
} return PTR_ERR(dspk->clk_dspk);
} }
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); regs = devm_platform_ioremap_resource(pdev, 0);
regs = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(regs)) if (IS_ERR(regs))
return PTR_ERR(regs); return PTR_ERR(regs);
dspk->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
&tegra186_dspk_regmap_config); dspk->regmap = devm_regmap_init_mmio(dev, regs, &tegra186_dspk_regmap);
if (IS_ERR(dspk->regmap)) { if (IS_ERR(dspk->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n"); dev_err(dev, "regmap init failed\n");
return PTR_ERR(dspk->regmap); return PTR_ERR(dspk->regmap);
} }
regcache_cache_only(dspk->regmap, true); regcache_cache_only(dspk->regmap, true);
pm_runtime_enable(&pdev->dev); err = devm_snd_soc_register_component(dev, &tegra186_dspk_cmpnt,
ret = snd_soc_register_codec(&pdev->dev, &tegra186_dspk_codec, tegra186_dspk_dais,
tegra186_dspk_dais, ARRAY_SIZE(tegra186_dspk_dais));
ARRAY_SIZE(tegra186_dspk_dais)); if (err) {
if (ret != 0) { dev_err(dev, "can't register DSPK component, err: %d\n",
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret); err);
pm_runtime_disable(&pdev->dev); return err;
return ret;
} }
if (of_property_read_string(np, "prod-name", &dspk->prod_name) == 0) { pm_runtime_enable(dev);
ret = tegra_pinctrl_config_prod(&pdev->dev, dspk->prod_name);
if (ret < 0)
dev_warn(&pdev->dev, "Failed to set %s setting\n",
dspk->prod_name);
}
return 0; return 0;
} }
static int tegra186_dspk_platform_remove(struct platform_device *pdev) static int tegra186_dspk_platform_remove(struct platform_device *pdev)
{ {
struct tegra186_dspk *dspk;
dspk = dev_get_drvdata(&pdev->dev);
snd_soc_unregister_codec(&pdev->dev);
pm_runtime_disable(&pdev->dev); pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
tegra186_dspk_runtime_suspend(&pdev->dev);
return 0; return 0;
} }
static const struct dev_pm_ops tegra186_dspk_pm_ops = { static const struct dev_pm_ops tegra186_dspk_pm_ops = {
SET_RUNTIME_PM_OPS(tegra186_dspk_runtime_suspend, SET_RUNTIME_PM_OPS(tegra186_dspk_runtime_suspend,
tegra186_dspk_runtime_resume, NULL) tegra186_dspk_runtime_resume, NULL)
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume) pm_runtime_force_resume)
}; };
static struct platform_driver tegra186_dspk_driver = { static struct platform_driver tegra186_dspk_driver = {
.driver = { .driver = {
.name = DRV_NAME, .name = "tegra186-dspk",
.owner = THIS_MODULE,
.of_match_table = tegra186_dspk_of_match, .of_match_table = tegra186_dspk_of_match,
.pm = &tegra186_dspk_pm_ops, .pm = &tegra186_dspk_pm_ops,
}, },
@@ -516,9 +504,7 @@ static struct platform_driver tegra186_dspk_driver = {
}; };
module_platform_driver(tegra186_dspk_driver); module_platform_driver(tegra186_dspk_driver);
MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>"); MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>");
MODULE_DESCRIPTION("Tegra186 DSPK ASoC driver"); MODULE_AUTHOR("Sameer Pujar <spujar@nvidia.com>");
MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Tegra186 ASoC DSPK driver");
MODULE_ALIAS("platform:" DRV_NAME); MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, tegra186_dspk_of_match);

217
sound/soc/tegra/tegra186_dspk.h
View File

@@ -1,182 +1,73 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* tegra186_dspk_alt.h - Definitions for Tegra186 DSPK driver * tegra186_dspk.h - Definitions for Tegra186 DSPK driver
* *
* Copyright (c) 2015-2019 NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#ifndef __TEGRA186_DSPK_ALT_H__ #ifndef __TEGRA186_DSPK_H__
#define __TEGRA186_DSPK_ALT_H__ #define __TEGRA186_DSPK_H__
/* Register offsets from DSPK BASE */ /* Register offsets from DSPK BASE */
#define TEGRA186_DSPK_AXBAR_RX_STATUS 0x0c #define TEGRA186_DSPK_RX_STATUS 0x0c
#define TEGRA186_DSPK_AXBAR_RX_INT_STATUS 0x10 #define TEGRA186_DSPK_RX_INT_STATUS 0x10
#define TEGRA186_DSPK_AXBAR_RX_INT_MASK 0x14 #define TEGRA186_DSPK_RX_INT_MASK 0x14
#define TEGRA186_DSPK_AXBAR_RX_INT_SET 0x18 #define TEGRA186_DSPK_RX_INT_SET 0x18
#define TEGRA186_DSPK_AXBAR_RX_INT_CLEAR 0x1c #define TEGRA186_DSPK_RX_INT_CLEAR 0x1c
#define TEGRA186_DSPK_AXBAR_RX_CIF_CTRL 0x20 #define TEGRA186_DSPK_RX_CIF_CTRL 0x20
#define TEGRA186_DSPK_AXBAR_RX_CYA 0x24 #define TEGRA186_DSPK_ENABLE 0x40
#define TEGRA186_DSPK_AXBAR_RX_CIF_FIFO_STATUS 0x28 #define TEGRA186_DSPK_SOFT_RESET 0x44
#define TEGRA186_DSPK_CG 0x48
#define TEGRA186_DSPK_ENABLE 0x40 #define TEGRA186_DSPK_STATUS 0x4c
#define TEGRA186_DSPK_SOFT_RESET 0x44 #define TEGRA186_DSPK_INT_STATUS 0x50
#define TEGRA186_DSPK_CG 0x48 #define TEGRA186_DSPK_CORE_CTRL 0x60
#define TEGRA186_DSPK_STATUS 0x4c #define TEGRA186_DSPK_CODEC_CTRL 0x64
#define TEGRA186_DSPK_INT_STATUS 0x50
#define TEGRA186_DSPK_CORE_CTRL 0x60
#define TEGRA186_DSPK_CODEC_CTRL 0x64
#define TEGRA186_DSPK_CODEC_DATA 0x68
#define TEGRA186_DSPK_CODEC_ENABLE 0x6c
#define TEGRA186_DSPK_CLK_TRIM 0x70
#define TEGRA186_DSPK_SDM_COEF_A_2 0x74
#define TEGRA186_DSPK_SDM_COEF_A_3 0x78
#define TEGRA186_DSPK_SDM_COEF_A_4 0x7c
#define TEGRA186_DSPK_SDM_COEF_A_5 0x80
#define TEGRA186_DSPK_SDM_COEF_C_1 0x84
#define TEGRA186_DSPK_SDM_COEF_C_2 0x88
#define TEGRA186_DSPK_SDM_COEF_C_3 0x8c
#define TEGRA186_DSPK_SDM_COEF_C_4 0x90
#define TEGRA186_DSPK_SDM_COEF_G_1 0x94
#define TEGRA186_DSPK_SDM_COEF_G_2 0x98
#define TEGRA186_DSPK_DEBUG_STATUS 0x9c
#define TEGRA186_DSPK_DEBUG_CIF_CNTR 0xa0
#define TEGRA186_DSPK_DEBUG_STAGE1_CNTR 0xa4
#define TEGRA186_DSPK_DEBUG_STAGE2_CNTR 0xa8
#define TEGRA186_DSPK_DEBUG_STAGE3_CNTR 0xac
#define TEGRA186_DSPK_DEBUG_STAGE4_CNTR 0xb0
/* Constants for DSPK */
#define TEGRA186_DSPK_OSR_32 0
#define TEGRA186_DSPK_OSR_64 1
#define TEGRA186_DSPK_OSR_128 2
#define TEGRA186_DSPK_OSR_256 3
/* DSPK ENABLE Register field */
#define TEGRA186_DSPK_ENABLE_EN BIT(0)
/* DSPK SOFT RESET field */
#define TEGRA186_DSPK_SOFT_RESET_EN BIT(0)
/* DSPK CG field */
#define TEGRA186_DSPK_CG_SLCG_EN BIT(0)
/* DSPK STATUS fields */
#define TEGRA186_DSPK_CODEC_CONFIG_DONE_SHIFT 14
#define TEGRA186_DSPK_CODEC_CONFIG_DONE_MASK (0x1 << TEGRA186_DSPK_CODEC_CONFIG_DONE_SHIFT)
#define TEGRA186_DSPK_SLCG_CLKEN_SHIFT 12
#define TEGRA186_DSPK_SLCG_CLKEN_MASK (0x1 << TEGRA186_DSPK_SLCG_CLKEN_SHIFT)
#define TEGRA186_DSPK_RX_CIF_FULL_SHIFT 10
#define TEGRA186_DSPK_RX_CIF_FULL_MASK (0x1 << TEGRA186_DSPK_RX_CIF_FULL_SHIFT)
#define TEGRA186_DSPK_RX_CIF_EMPTY_SHIFT 9
#define TEGRA186_DSPK_RX_CIF_EMPTY_MASK (0x1 << TEGRA186_DSPK_RX_CIF_EMPTY_SHIFT)
#define TEGRA186_DSPK_RX_ENABLED_SHIFT 8
#define TEGRA186_DSPK_RX_ENABLED_MASK (0x1 << TEGRA186_DSPK_RX_ENABLED_SHIFT)
/* DSPK INT STATUS fields */
#define TEGRA186_DSPK_INT_CODEC_CONFIG_DONE_SHIFT 12
#define TEGRA186_DSPK_INT_CODEC_CONFIG_DONE_MASK (0x1 << TEGRA186_DSPK_INT_CODEC_CONFIG_DONE_SHIFT)
#define TEGRA186_DSPK_RX_CIF_FIFO_UNDERRUN_SHIFT 9
#define TEGRA186_DSPK_RX_CIF_FIFO_UNDERRUN_MASK (0x1 << TEGRA186_DSPK_RX_CIF_FIFO_UNDERRUN_SHIFT)
#define TEGRA186_DSPK_RX_DONE_SHIFT 8
#define TEGRA186_DSPK_RX_DONE_MASK (0x1 << TEGRA186_DSPK_RX_DONE_SHIFT)
/* DSPK CORE CONTROL fields */ /* DSPK CORE CONTROL fields */
#define TEGRA186_DSPK_GAIN1_SHIFT 28 #define CH_SEL_SHIFT 8
#define TEGRA186_DSPK_GAIN1_MASK (0x7 << TEGRA186_DSPK_GAIN1_SHIFT) #define TEGRA186_DSPK_CHANNEL_SELECT_MASK (0x3 << CH_SEL_SHIFT)
#define DSPK_OSR_SHIFT 4
#define TEGRA186_DSPK_OSR_MASK (0x3 << DSPK_OSR_SHIFT)
#define LRSEL_POL_SHIFT 0
#define TEGRA186_DSPK_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT)
#define TEGRA186_DSPK_RX_FIFO_DEPTH 64
#define TEGRA186_DSPK_GAIN2_SHIFT 24 #define DSPK_OSR_FACTOR 32
#define TEGRA186_DSPK_GAIN2_MASK (0x7 << TEGRA186_DSPK_GAIN2_SHIFT)
#define TEGRA186_DSPK_GAIN3_SHIFT 20 /* DSPK interface clock ratio */
#define TEGRA186_DSPK_GAIN3_MASK (0x7 << TEGRA186_DSPK_GAIN3_SHIFT) #define DSPK_CLK_RATIO 4
#define TEGRA186_DSPK_FILTER_MODE_SHIFT 16 enum tegra_dspk_osr {
#define TEGRA186_DSPK_FILTER_MODE_MASK (0x1 << TEGRA186_DSPK_FILTER_MODE_SHIFT) DSPK_OSR_32,
DSPK_OSR_64,
DSPK_OSR_128,
DSPK_OSR_256,
};
#define TEGRA186_DSPK_CHANNEL_SELECT_SHIFT 8 enum tegra_dspk_ch_sel {
#define TEGRA186_DSPK_CHANNEL_SELECT_MASK (0x3 << TEGRA186_DSPK_CHANNEL_SELECT_SHIFT) DSPK_CH_SELECT_LEFT,
DSPK_CH_SELECT_RIGHT,
DSPK_CH_SELECT_STEREO,
};
#define TEGRA186_DSPK_OSR_SHIFT 4 enum tegra_dspk_lrsel {
#define TEGRA186_DSPK_OSR_MASK (0x3 << TEGRA186_DSPK_OSR_SHIFT) DSPK_LRSEL_LEFT,
DSPK_LRSEL_RIGHT,
#define TEGRA186_DSPK_LRSEL_POLARITY_SHIFT 0 };
#define TEGRA186_DSPK_LRSEL_POLARITY_MASK (0x1 << TEGRA186_DSPK_LRSEL_POLARITY_SHIFT)
/* DSPK CODEC CONTROL fileds */
#define TEGRA186_DSPK_CODEC_CHANNEL_SELECT_SHIFT 24
#define TEGRA186_DSPK_CODEC_CHANNEL_SELECT_MASK (0x3 << TEGRA186_DSPK_CODEC_CHANNEL_SELECT_SHIFT)
#define TEGRA186_DSPK_CODEC_BIT_ORDER_SHIFT 16
#define TEGRA186_DSPK_CODEC_BIT_MASK (0x1 << TEGRA186_DSPK_CODEC_BIT_ORDER_SHIFT)
#define TEGRA186_DSPK_CODEC_CONFIG_MODE_SHIFT 12
#define TEGRA186_DSPK_CODEC_CONFIG_MODE_MASK (0x1 << TEGRA186_DSPK_CODEC_CONFIG_MODE_SHIFT)
#define TEGRA186_DSPK_CODEC_CONFIG_REP_NUM_SHIFT 0
#define TEGRA186_DSPK_CODEC_CONFIG_REP_NUM_MASK (0xff << TEGRA186_DSPK_CODEC_CONFIG_REP_NUM_SHIFT)
/* DSPK CODEC ENABLE fields */
#define TEGRA186_DSPK_CODEC_ENABLE_SHIFT 0
#define TEGRA186_DSPK_CODEC_ENABLE_MASK (0x1 << TEGRA186_DSPK_CODEC_ENABLE_SHIFT)
/* DSPL CLK TRIM field */
#define TEGRA186_DSPK_CLK_TRIM_SHIFT 0
#define TEGRA186_DSPK_CLK_TRIM_MASK (0x1f << TEGRA186_DSPK_CLK_TRIM_SHIFT)
/* DSPK DEBUG Register fields*/
#define TEGRA186_DSPK_DEBUG_STATUS_SHIFT 0
#define TEGRA186_DSPK_DEBUG_STATUS_MASK (0xff << TEGRA186_DSPK_DEBUG_STATUS_SHIFT)
#define TEGRA186_DSPK_DEBUG_CIF_CH0_SHIFT 16
#define TEGRA186_DSPK_DEBUG_CIF_CH0_MASK (0xffff << TEGRA186_DSPK_DEBUG_CIF_CH0_SHIFT)
#define TEGRA186_DSPK_DEBUG_CIF_CH1_SHIFT 0
#define TEGRA186_DSPK_DEBUG_CIF_CH1_MASK (0xffff << TEGRA186_DSPK_DEBUG_CIF_CH1_SHIFT)
#define TEGRA186_DSPK_DEBUG_STAGE1_CH0_SHIFT 16
#define TEGRA186_DSPK_DEBUG_STAGE1_CH0_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE1_CH0_SHIFT)
#define TEGRA186_DSPK_DEBUG_STAGE1_CH1_SHIFT 0
#define TEGRA186_DSPK_DEBUG_STAGE1_CH1_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE1_CH1_SHIFT)
#define TEGRA186_DSPK_DEBUG_STAGE2_CH0_SHIFT 16
#define TEGRA186_DSPK_DEBUG_STAGE2_CH0_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE2_CH0_SHIFT)
#define TEGRA186_DSPK_DEBUG_STAGE2_CH1_SHIFT 0
#define TEGRA186_DSPK_DEBUG_STAGE2_CH1_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE2_CH1_SHIFT)
#define TEGRA186_DSPK_DEBUG_STAGE3_CH0_SHIFT 16
#define TEGRA186_DSPK_DEBUG_STAGE3_CH0_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE3_CH0_SHIFT)
#define TEGRA186_DSPK_DEBUG_STAGE3_CH1_SHIFT 0
#define TEGRA186_DSPK_DEBUG_STAGE3_CH1_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE3_CH1_SHIFT)
#define TEGRA186_DSPK_DEBUG_STAGE4_CH0_SHIFT 16
#define TEGRA186_DSPK_DEBUG_STAGE4_CH0_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE4_CH0_SHIFT)
#define TEGRA186_DSPK_DEBUG_STAGE4_CH1_SHIFT 0
#define TEGRA186_DSPK_DEBUG_STAGE4_CH1_MASK (0xffff << TEGRA186_DSPK_DEBUG_STAGE4_CH1_SHIFT)
#define TEGRA186_DSPK_RX_FIFO_DEPTH 4
struct tegra186_dspk { struct tegra186_dspk {
struct clk *clk_dspk; unsigned int rx_fifo_th;
struct regmap *regmap; unsigned int osr_val;
const char *prod_name; unsigned int lrsel;
unsigned int rx_fifo_th; /* threshold in terms of frames */ unsigned int srate_override;
unsigned int osr_val; /* osr value */ unsigned int audio_ch_override;
unsigned int ch_sel; /* Used for client channel override */
unsigned int audio_fmt_override;
unsigned int mono_to_stereo;
unsigned int stereo_to_mono;
struct clk *clk_dspk;
struct regmap *regmap;
}; };
#endif #endif

888
sound/soc/tegra/tegra210_admaif.c
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File diff suppressed because it is too large Load Diff

289
sound/soc/tegra/tegra210_admaif.h
View File

@@ -1,156 +1,132 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* tegra210_admaif_alt.h - Tegra ADMAIF registers * tegra210_admaif.h - Tegra ADMAIF registers
* *
* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#ifndef __TEGRA_ADMAIF_ALT_H__ #ifndef __TEGRA_ADMAIF_H__
#define __TEGRA_ADMAIF_ALT_H__ #define __TEGRA_ADMAIF_H__
#define TEGRA_ADMAIF_CHANNEL_REG_STRIDE 0x40 #define TEGRA_ADMAIF_CHANNEL_REG_STRIDE 0x40
/* Tegra210 specific */
#define TEGRA210_ADMAIF_LAST_REG 0x75f #define TEGRA210_ADMAIF_LAST_REG 0x75f
#define TEGRA186_ADMAIF_LAST_REG 0xd5f #define TEGRA210_ADMAIF_CHANNEL_COUNT 10
#define TEGRA210_ADMAIF_RX_BASE 0x0
#define TEGRA210_ADMAIF_CHANNEL_COUNT 10 #define TEGRA210_ADMAIF_TX_BASE 0x300
#define TEGRA186_ADMAIF_CHANNEL_COUNT 20 #define TEGRA210_ADMAIF_GLOBAL_BASE 0x700
/* Tegra186 specific */
#define TEGRA210_ADMAIF_XBAR_RX_BASE 0x0 #define TEGRA186_ADMAIF_LAST_REG 0xd5f
#define TEGRA210_ADMAIF_XBAR_TX_BASE 0x300 #define TEGRA186_ADMAIF_CHANNEL_COUNT 20
#define TEGRA210_ADMAIF_GLOBAL_BASE 0x700 #define TEGRA186_ADMAIF_RX_BASE 0x0
#define TEGRA186_ADMAIF_TX_BASE 0x500
#define TEGRA186_ADMAIF_XBAR_RX_BASE 0x0 #define TEGRA186_ADMAIF_GLOBAL_BASE 0xd00
#define TEGRA186_ADMAIF_XBAR_TX_BASE 0x500 /* Global registers */
#define TEGRA186_ADMAIF_GLOBAL_BASE 0xd00 #define TEGRA_ADMAIF_GLOBAL_ENABLE 0x0
#define TEGRA_ADMAIF_GLOBAL_CG_0 0x8
#define TEGRA_ADMAIF_XBAR_RX_ENABLE 0x0 #define TEGRA_ADMAIF_GLOBAL_STATUS 0x10
#define TEGRA_ADMAIF_XBAR_RX_SOFT_RESET 0x4 #define TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS 0x20
#define TEGRA_ADMAIF_XBAR_RX_STATUS 0xc #define TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS 0x24
#define TEGRA_ADMAIF_XBAR_RX_INT_STATUS 0x10 /* RX channel registers */
#define TEGRA_ADMAIF_XBAR_RX_INT_MASK 0x14 #define TEGRA_ADMAIF_RX_ENABLE 0x0
#define TEGRA_ADMAIF_XBAR_RX_INT_SET 0x18 #define TEGRA_ADMAIF_RX_SOFT_RESET 0x4
#define TEGRA_ADMAIF_XBAR_RX_INT_CLEAR 0x1c #define TEGRA_ADMAIF_RX_STATUS 0xc
#define TEGRA_ADMAIF_CHAN_ACIF_RX_CTRL 0x20 #define TEGRA_ADMAIF_RX_INT_STATUS 0x10
#define TEGRA_ADMAIF_XBAR_RX_FIFO_CTRL 0x28 #define TEGRA_ADMAIF_RX_INT_MASK 0x14
#define TEGRA_ADMAIF_XBAR_RX_FIFO_READ 0x2c #define TEGRA_ADMAIF_RX_INT_SET 0x18
#define TEGRA_ADMAIF_GLOBAL_ENABLE 0x0 #define TEGRA_ADMAIF_RX_INT_CLEAR 0x1c
#define TEGRA_ADMAIF_GLOBAL_CG_0 0x8 #define TEGRA_ADMAIF_CH_ACIF_RX_CTRL 0x20
#define TEGRA_ADMAIF_GLOBAL_STATUS 0x10 #define TEGRA_ADMAIF_RX_FIFO_CTRL 0x28
#define TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS 0x20 #define TEGRA_ADMAIF_RX_FIFO_READ 0x2c
#define TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS 0x24 /* TX channel registers */
#define TEGRA_ADMAIF_TX_ENABLE 0x0
#define TEGRA_ADMAIF_XBAR_TX_ENABLE 0x0 #define TEGRA_ADMAIF_TX_SOFT_RESET 0x4
#define TEGRA_ADMAIF_XBAR_TX_SOFT_RESET 0x4 #define TEGRA_ADMAIF_TX_STATUS 0xc
#define TEGRA_ADMAIF_XBAR_TX_STATUS 0xc #define TEGRA_ADMAIF_TX_INT_STATUS 0x10
#define TEGRA_ADMAIF_XBAR_TX_INT_STATUS 0x10 #define TEGRA_ADMAIF_TX_INT_MASK 0x14
#define TEGRA_ADMAIF_XBAR_TX_INT_MASK 0x14 #define TEGRA_ADMAIF_TX_INT_SET 0x18
#define TEGRA_ADMAIF_XBAR_TX_INT_SET 0x18 #define TEGRA_ADMAIF_TX_INT_CLEAR 0x1c
#define TEGRA_ADMAIF_XBAR_TX_INT_CLEAR 0x1c #define TEGRA_ADMAIF_CH_ACIF_TX_CTRL 0x20
#define TEGRA_ADMAIF_CHAN_ACIF_TX_CTRL 0x20 #define TEGRA_ADMAIF_TX_FIFO_CTRL 0x28
#define TEGRA_ADMAIF_XBAR_TX_FIFO_CTRL 0x28 #define TEGRA_ADMAIF_TX_FIFO_WRITE 0x2c
#define TEGRA_ADMAIF_XBAR_TX_FIFO_WRITE 0x2c /* Bit fields */
#define PACK8_EN_SHIFT 31
#define TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK8_EN_SHIFT 31 #define PACK8_EN_MASK BIT(PACK8_EN_SHIFT)
#define TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK8_EN_MASK \ #define PACK8_EN BIT(PACK8_EN_SHIFT)
(1 << TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK8_EN_SHIFT) #define PACK16_EN_SHIFT 30
#define TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK8_EN \ #define PACK16_EN_MASK BIT(PACK16_EN_SHIFT)
(1 << TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK8_EN_SHIFT) #define PACK16_EN BIT(PACK16_EN_SHIFT)
#define TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK16_EN_SHIFT 30 #define TX_ENABLE_SHIFT 0
#define TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK16_EN_MASK \ #define TX_ENABLE_MASK BIT(TX_ENABLE_SHIFT)
(1 << TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK16_EN_SHIFT) #define TX_ENABLE BIT(TX_ENABLE_SHIFT)
#define TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK16_EN \ #define RX_ENABLE_SHIFT 0
(1 << TEGRA_ADMAIF_CHAN_ACIF_CTRL_PACK16_EN_SHIFT) #define RX_ENABLE_MASK BIT(RX_ENABLE_SHIFT)
#define RX_ENABLE BIT(RX_ENABLE_SHIFT)
#define TEGRA_ADMAIF_XBAR_TX_ENABLE_SHIFT 0 #define SW_RESET_MASK 1
#define TEGRA_ADMAIF_XBAR_TX_EN \ #define SW_RESET 1
(1 << TEGRA_ADMAIF_XBAR_TX_ENABLE_SHIFT) /* Default values - Tegra210 */
#define TEGRA_ADMAIF_XBAR_TX_ENABLE_MASK \ #define TEGRA210_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300
(1 << TEGRA_ADMAIF_XBAR_TX_ENABLE_SHIFT) #define TEGRA210_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304
#define TEGRA210_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000208
#define TEGRA_ADMAIF_XBAR_RX_ENABLE_SHIFT 0 #define TEGRA210_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000020b
#define TEGRA_ADMAIF_XBAR_RX_EN \ #define TEGRA210_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000020e
(1 << TEGRA_ADMAIF_XBAR_RX_ENABLE_SHIFT) #define TEGRA210_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000211
#define TEGRA_ADMAIF_XBAR_RX_ENABLE_MASK \ #define TEGRA210_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000214
(1 << TEGRA_ADMAIF_XBAR_RX_ENABLE_SHIFT) #define TEGRA210_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000217
#define TEGRA210_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021a
#define SW_RESET_MASK 1 #define TEGRA210_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021d
#define SW_RESET 1 #define TEGRA210_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300
#define TEGRA210_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304
#define TEGRA210_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300 #define TEGRA210_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x01800208
#define TEGRA210_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304 #define TEGRA210_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0180020b
#define TEGRA210_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000208 #define TEGRA210_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0180020e
#define TEGRA210_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000020b #define TEGRA210_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800211
#define TEGRA210_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000020e #define TEGRA210_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800214
#define TEGRA210_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000211 #define TEGRA210_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800217
#define TEGRA210_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000214 #define TEGRA210_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021a
#define TEGRA210_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000217 #define TEGRA210_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021d
#define TEGRA210_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021a /* Default values - Tegra186 */
#define TEGRA210_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021d #define TEGRA186_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300
#define TEGRA186_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304
#define TEGRA210_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300 #define TEGRA186_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000308
#define TEGRA210_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304 #define TEGRA186_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000030c
#define TEGRA210_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x01800208 #define TEGRA186_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x00000210
#define TEGRA210_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0180020b #define TEGRA186_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000213
#define TEGRA210_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0180020e #define TEGRA186_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000216
#define TEGRA210_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800211 #define TEGRA186_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000219
#define TEGRA210_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800214 #define TEGRA186_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021c
#define TEGRA210_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800217 #define TEGRA186_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021f
#define TEGRA210_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021a #define TEGRA186_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT 0x00000222
#define TEGRA210_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021d #define TEGRA186_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT 0x00000225
#define TEGRA186_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT 0x00000228
#define TEGRA186_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300 #define TEGRA186_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT 0x0000022b
#define TEGRA186_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304 #define TEGRA186_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT 0x0000022e
#define TEGRA186_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000308 #define TEGRA186_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT 0x00000231
#define TEGRA186_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000030c #define TEGRA186_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT 0x00000234
#define TEGRA186_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x00000210 #define TEGRA186_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT 0x00000237
#define TEGRA186_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000213 #define TEGRA186_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT 0x0000023a
#define TEGRA186_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000216 #define TEGRA186_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT 0x0000023d
#define TEGRA186_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000219 #define TEGRA186_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300
#define TEGRA186_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021c #define TEGRA186_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304
#define TEGRA186_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021f #define TEGRA186_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x02000308
#define TEGRA186_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT 0x00000222 #define TEGRA186_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0200030c
#define TEGRA186_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT 0x00000225 #define TEGRA186_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x01800210
#define TEGRA186_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT 0x00000228 #define TEGRA186_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800213
#define TEGRA186_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT 0x0000022b #define TEGRA186_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800216
#define TEGRA186_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT 0x0000022e #define TEGRA186_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800219
#define TEGRA186_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT 0x00000231 #define TEGRA186_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021c
#define TEGRA186_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT 0x00000234 #define TEGRA186_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021f
#define TEGRA186_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT 0x00000237 #define TEGRA186_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT 0x01800222
#define TEGRA186_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT 0x0000023a #define TEGRA186_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT 0x01800225
#define TEGRA186_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT 0x0000023d #define TEGRA186_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT 0x01800228
#define TEGRA186_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT 0x0180022b
#define TEGRA186_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300 #define TEGRA186_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT 0x0180022e
#define TEGRA186_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304 #define TEGRA186_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT 0x01800231
#define TEGRA186_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x02000308 #define TEGRA186_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT 0x01800234
#define TEGRA186_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0200030c #define TEGRA186_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT 0x01800237
#define TEGRA186_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x01800210 #define TEGRA186_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT 0x0180023a
#define TEGRA186_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800213 #define TEGRA186_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT 0x0180023d
#define TEGRA186_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800216
#define TEGRA186_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800219
#define TEGRA186_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021c
#define TEGRA186_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021f
#define TEGRA186_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT 0x01800222
#define TEGRA186_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT 0x01800225
#define TEGRA186_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT 0x01800228
#define TEGRA186_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT 0x0180022b
#define TEGRA186_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT 0x0180022e
#define TEGRA186_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT 0x01800231
#define TEGRA186_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT 0x01800234
#define TEGRA186_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT 0x01800237
#define TEGRA186_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT 0x0180023a
#define TEGRA186_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT 0x0180023d
enum { enum {
DATA_8BIT, DATA_8BIT,
@@ -165,31 +141,24 @@ enum {
}; };
struct tegra_admaif_soc_data { struct tegra_admaif_soc_data {
unsigned int num_ch; const struct snd_soc_component_driver *cmpnt;
struct snd_soc_dai_driver *codec_dais;
struct snd_soc_codec_driver *admaif_codec;
const struct regmap_config *regmap_conf; const struct regmap_config *regmap_conf;
bool is_isomgr_client; struct snd_soc_dai_driver *dais;
unsigned int global_base; unsigned int global_base;
unsigned int tx_base; unsigned int tx_base;
unsigned int rx_base; unsigned int rx_base;
unsigned int num_ch;
}; };
struct tegra_admaif { struct tegra_admaif {
/* regmap for admaif */ struct snd_dmaengine_dai_dma_data *capture_dma_data;
struct regmap *regmap; struct snd_dmaengine_dai_dma_data *playback_dma_data;
struct device *dev;
struct tegra_alt_pcm_dma_params *capture_dma_data;
struct tegra_alt_pcm_dma_params *playback_dma_data;
const struct tegra_admaif_soc_data *soc_data; const struct tegra_admaif_soc_data *soc_data;
unsigned int *audio_ch_override[ADMAIF_PATHS]; unsigned int *audio_ch_override[ADMAIF_PATHS];
unsigned int *client_ch_override[ADMAIF_PATHS]; unsigned int *client_ch_override[ADMAIF_PATHS];
unsigned int *mono_to_stereo[ADMAIF_PATHS]; unsigned int *mono_to_stereo[ADMAIF_PATHS];
unsigned int *stereo_to_mono[ADMAIF_PATHS]; unsigned int *stereo_to_mono[ADMAIF_PATHS];
int reg_dump_flag; struct regmap *regmap;
void __iomem *base_addr;
}; };
extern void tegra_adma_dump_ch_reg(void);
#endif #endif

651
sound/soc/tegra/tegra210_ahub.c Normal file
View File

@@ -0,0 +1,651 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* tegra210_ahub.c - Tegra210 AHUB driver
*
* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
*
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "tegra210_ahub.h"
static int tegra_ahub_get_value_enum(struct snd_kcontrol *kctl,
struct snd_ctl_elem_value *uctl)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl);
struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt);
struct soc_enum *e = (struct soc_enum *)kctl->private_value;
unsigned int reg, i, bit_pos = 0;
/*
* Find the bit position of current MUX input.
* If nothing is set, position would be 0 and it corresponds to 'None'.
*/
for (i = 0; i < ahub->soc_data->reg_count; i++) {
unsigned int reg_val;
reg = e->reg + (TEGRA210_XBAR_PART1_RX * i);
snd_soc_component_read(cmpnt, reg, &reg_val);
reg_val &= ahub->soc_data->mask[i];
if (reg_val) {
bit_pos = ffs(reg_val) +
(8 * cmpnt->val_bytes * i);
break;
}
}
/* Find index related to the item in array *_ahub_mux_texts[] */
for (i = 0; i < e->items; i++) {
if (bit_pos == e->values[i]) {
uctl->value.enumerated.item[0] = i;
break;
}
}
return 0;
}
static int tegra_ahub_put_value_enum(struct snd_kcontrol *kctl,
struct snd_ctl_elem_value *uctl)
{
struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_component(kctl);
struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt);
struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kctl);
struct soc_enum *e = (struct soc_enum *)kctl->private_value;
struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG] = { };
unsigned int *item = uctl->value.enumerated.item;
unsigned int value = e->values[item[0]];
unsigned int i, bit_pos, reg_idx = 0, reg_val = 0;
if (item[0] >= e->items)
return -EINVAL;
if (value) {
/* Get the register index and value to set */
reg_idx = (value - 1) / (8 * cmpnt->val_bytes);
bit_pos = (value - 1) % (8 * cmpnt->val_bytes);
reg_val = BIT(bit_pos);
}
/*
* Run through all parts of a MUX register to find the state changes.
* There will be an additional update if new MUX input value is from
* different part of the MUX register.
*/
for (i = 0; i < ahub->soc_data->reg_count; i++) {
update[i].reg = e->reg + (TEGRA210_XBAR_PART1_RX * i);
update[i].val = (i == reg_idx) ? reg_val : 0;
update[i].mask = ahub->soc_data->mask[i];
update[i].kcontrol = kctl;
/* Update widget power if state has changed */
if (snd_soc_component_test_bits(cmpnt, update[i].reg,
update[i].mask, update[i].val))
snd_soc_dapm_mux_update_power(dapm, kctl, item[0], e,
&update[i]);
}
return 0;
}
static struct snd_soc_dai_driver tegra210_ahub_dais[] = {
DAI(ADMAIF1),
DAI(ADMAIF2),
DAI(ADMAIF3),
DAI(ADMAIF4),
DAI(ADMAIF5),
DAI(ADMAIF6),
DAI(ADMAIF7),
DAI(ADMAIF8),
DAI(ADMAIF9),
DAI(ADMAIF10),
DAI(I2S1),
DAI(I2S2),
DAI(I2S3),
DAI(I2S4),
DAI(I2S5),
DAI(DMIC1),
DAI(DMIC2),
DAI(DMIC3),
};
static struct snd_soc_dai_driver tegra186_ahub_dais[] = {
DAI(ADMAIF1),
DAI(ADMAIF2),
DAI(ADMAIF3),
DAI(ADMAIF4),
DAI(ADMAIF5),
DAI(ADMAIF6),
DAI(ADMAIF7),
DAI(ADMAIF8),
DAI(ADMAIF9),
DAI(ADMAIF10),
DAI(ADMAIF11),
DAI(ADMAIF12),
DAI(ADMAIF13),
DAI(ADMAIF14),
DAI(ADMAIF15),
DAI(ADMAIF16),
DAI(ADMAIF17),
DAI(ADMAIF18),
DAI(ADMAIF19),
DAI(ADMAIF20),
DAI(I2S1),
DAI(I2S2),
DAI(I2S3),
DAI(I2S4),
DAI(I2S5),
DAI(I2S6),
DAI(DMIC1),
DAI(DMIC2),
DAI(DMIC3),
DAI(DMIC4),
DAI(DSPK1),
DAI(DSPK2),
};
static const char * const tegra210_ahub_mux_texts[] = {
"None",
"ADMAIF1",
"ADMAIF2",
"ADMAIF3",
"ADMAIF4",
"ADMAIF5",
"ADMAIF6",
"ADMAIF7",
"ADMAIF8",
"ADMAIF9",
"ADMAIF10",
"I2S1",
"I2S2",
"I2S3",
"I2S4",
"I2S5",
"DMIC1",
"DMIC2",
"DMIC3",
};
static const char * const tegra186_ahub_mux_texts[] = {
"None",
"ADMAIF1",
"ADMAIF2",
"ADMAIF3",
"ADMAIF4",
"ADMAIF5",
"ADMAIF6",
"ADMAIF7",
"ADMAIF8",
"ADMAIF9",
"ADMAIF10",
"ADMAIF11",
"ADMAIF12",
"ADMAIF13",
"ADMAIF14",
"ADMAIF15",
"ADMAIF16",
"I2S1",
"I2S2",
"I2S3",
"I2S4",
"I2S5",
"I2S6",
"ADMAIF17",
"ADMAIF18",
"ADMAIF19",
"ADMAIF20",
"DMIC1",
"DMIC2",
"DMIC3",
"DMIC4",
};
static const unsigned int tegra210_ahub_mux_values[] = {
0,
MUX_VALUE(0, 0),
MUX_VALUE(0, 1),
MUX_VALUE(0, 2),
MUX_VALUE(0, 3),
MUX_VALUE(0, 4),
MUX_VALUE(0, 5),
MUX_VALUE(0, 6),
MUX_VALUE(0, 7),
MUX_VALUE(0, 8),
MUX_VALUE(0, 9),
MUX_VALUE(0, 16),
MUX_VALUE(0, 17),
MUX_VALUE(0, 18),
MUX_VALUE(0, 19),
MUX_VALUE(0, 20),
};
static const unsigned int tegra186_ahub_mux_values[] = {
0,
MUX_VALUE(0, 0),
MUX_VALUE(0, 1),
MUX_VALUE(0, 2),
MUX_VALUE(0, 3),
MUX_VALUE(0, 4),
MUX_VALUE(0, 5),
MUX_VALUE(0, 6),
MUX_VALUE(0, 7),
MUX_VALUE(0, 8),
MUX_VALUE(0, 9),
MUX_VALUE(0, 10),
MUX_VALUE(0, 11),
MUX_VALUE(0, 12),
MUX_VALUE(0, 13),
MUX_VALUE(0, 14),
MUX_VALUE(0, 15),
MUX_VALUE(0, 16),
MUX_VALUE(0, 17),
MUX_VALUE(0, 18),
MUX_VALUE(0, 19),
MUX_VALUE(0, 20),
MUX_VALUE(0, 21),
MUX_VALUE(3, 16),
MUX_VALUE(3, 17),
MUX_VALUE(3, 18),
MUX_VALUE(3, 19),
MUX_VALUE(2, 18),
MUX_VALUE(2, 19),
MUX_VALUE(2, 20),
MUX_VALUE(2, 21),
};
/* Controls for t210 */
MUX_ENUM_CTRL_DECL(t210_admaif1_tx, 0x00);
MUX_ENUM_CTRL_DECL(t210_admaif2_tx, 0x01);
MUX_ENUM_CTRL_DECL(t210_admaif3_tx, 0x02);
MUX_ENUM_CTRL_DECL(t210_admaif4_tx, 0x03);
MUX_ENUM_CTRL_DECL(t210_admaif5_tx, 0x04);
MUX_ENUM_CTRL_DECL(t210_admaif6_tx, 0x05);
MUX_ENUM_CTRL_DECL(t210_admaif7_tx, 0x06);
MUX_ENUM_CTRL_DECL(t210_admaif8_tx, 0x07);
MUX_ENUM_CTRL_DECL(t210_admaif9_tx, 0x08);
MUX_ENUM_CTRL_DECL(t210_admaif10_tx, 0x09);
MUX_ENUM_CTRL_DECL(t210_i2s1_tx, 0x10);
MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11);
MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12);
MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13);
MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14);
/* Controls for t186 */
MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00);
MUX_ENUM_CTRL_DECL_186(t186_admaif2_tx, 0x01);
MUX_ENUM_CTRL_DECL_186(t186_admaif3_tx, 0x02);
MUX_ENUM_CTRL_DECL_186(t186_admaif4_tx, 0x03);
MUX_ENUM_CTRL_DECL_186(t186_admaif5_tx, 0x04);
MUX_ENUM_CTRL_DECL_186(t186_admaif6_tx, 0x05);
MUX_ENUM_CTRL_DECL_186(t186_admaif7_tx, 0x06);
MUX_ENUM_CTRL_DECL_186(t186_admaif8_tx, 0x07);
MUX_ENUM_CTRL_DECL_186(t186_admaif9_tx, 0x08);
MUX_ENUM_CTRL_DECL_186(t186_admaif10_tx, 0x09);
MUX_ENUM_CTRL_DECL_186(t186_i2s1_tx, 0x10);
MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11);
MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12);
MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13);
MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14);
MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a);
MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b);
MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c);
MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d);
MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e);
MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f);
MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15);
MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30);
MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31);
MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68);
MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69);
MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a);
MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b);
/*
* The number of entries in, and order of, this array is closely tied to the
* calculation of tegra210_ahub_codec.num_dapm_widgets near the end of
* tegra210_ahub_probe()
*/
static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = {
WIDGETS("ADMAIF1", t210_admaif1_tx),
WIDGETS("ADMAIF2", t210_admaif2_tx),
WIDGETS("ADMAIF3", t210_admaif3_tx),
WIDGETS("ADMAIF4", t210_admaif4_tx),
WIDGETS("ADMAIF5", t210_admaif5_tx),
WIDGETS("ADMAIF6", t210_admaif6_tx),
WIDGETS("ADMAIF7", t210_admaif7_tx),
WIDGETS("ADMAIF8", t210_admaif8_tx),
WIDGETS("ADMAIF9", t210_admaif9_tx),
WIDGETS("ADMAIF10", t210_admaif10_tx),
WIDGETS("I2S1", t210_i2s1_tx),
WIDGETS("I2S2", t210_i2s2_tx),
WIDGETS("I2S3", t210_i2s3_tx),
WIDGETS("I2S4", t210_i2s4_tx),
WIDGETS("I2S5", t210_i2s5_tx),
TX_WIDGETS("DMIC1"),
TX_WIDGETS("DMIC2"),
TX_WIDGETS("DMIC3"),
};
static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = {
WIDGETS("ADMAIF1", t186_admaif1_tx),
WIDGETS("ADMAIF2", t186_admaif2_tx),
WIDGETS("ADMAIF3", t186_admaif3_tx),
WIDGETS("ADMAIF4", t186_admaif4_tx),
WIDGETS("ADMAIF5", t186_admaif5_tx),
WIDGETS("ADMAIF6", t186_admaif6_tx),
WIDGETS("ADMAIF7", t186_admaif7_tx),
WIDGETS("ADMAIF8", t186_admaif8_tx),
WIDGETS("ADMAIF9", t186_admaif9_tx),
WIDGETS("ADMAIF10", t186_admaif10_tx),
WIDGETS("ADMAIF11", t186_admaif11_tx),
WIDGETS("ADMAIF12", t186_admaif12_tx),
WIDGETS("ADMAIF13", t186_admaif13_tx),
WIDGETS("ADMAIF14", t186_admaif14_tx),
WIDGETS("ADMAIF15", t186_admaif15_tx),
WIDGETS("ADMAIF16", t186_admaif16_tx),
WIDGETS("ADMAIF17", t186_admaif17_tx),
WIDGETS("ADMAIF18", t186_admaif18_tx),
WIDGETS("ADMAIF19", t186_admaif19_tx),
WIDGETS("ADMAIF20", t186_admaif20_tx),
WIDGETS("I2S1", t186_i2s1_tx),
WIDGETS("I2S2", t186_i2s2_tx),
WIDGETS("I2S3", t186_i2s3_tx),
WIDGETS("I2S4", t186_i2s4_tx),
WIDGETS("I2S5", t186_i2s5_tx),
WIDGETS("I2S6", t186_i2s6_tx),
TX_WIDGETS("DMIC1"),
TX_WIDGETS("DMIC2"),
TX_WIDGETS("DMIC3"),
TX_WIDGETS("DMIC4"),
WIDGETS("DSPK1", t186_dspk1_tx),
WIDGETS("DSPK2", t186_dspk2_tx),
};
#define TEGRA_COMMON_ROUTES(name) \
{ name " RX", NULL, name " Receive" }, \
{ name " Transmit", NULL, name " TX" }, \
{ name " TX", NULL, name " Mux" }, \
{ name " Mux", "ADMAIF1", "ADMAIF1 RX" }, \
{ name " Mux", "ADMAIF2", "ADMAIF2 RX" }, \
{ name " Mux", "ADMAIF3", "ADMAIF3 RX" }, \
{ name " Mux", "ADMAIF4", "ADMAIF4 RX" }, \
{ name " Mux", "ADMAIF5", "ADMAIF5 RX" }, \
{ name " Mux", "ADMAIF6", "ADMAIF6 RX" }, \
{ name " Mux", "ADMAIF7", "ADMAIF7 RX" }, \
{ name " Mux", "ADMAIF8", "ADMAIF8 RX" }, \
{ name " Mux", "ADMAIF9", "ADMAIF9 RX" }, \
{ name " Mux", "ADMAIF10", "ADMAIF10 RX" }, \
{ name " Mux", "I2S1", "I2S1 RX" }, \
{ name " Mux", "I2S2", "I2S2 RX" }, \
{ name " Mux", "I2S3", "I2S3 RX" }, \
{ name " Mux", "I2S4", "I2S4 RX" }, \
{ name " Mux", "I2S5", "I2S5 RX" }, \
{ name " Mux", "DMIC1", "DMIC1 RX" }, \
{ name " Mux", "DMIC2", "DMIC2 RX" }, \
{ name " Mux", "DMIC3", "DMIC3 RX" },
#define TEGRA186_ONLY_ROUTES(name) \
{ name " Mux", "ADMAIF11", "ADMAIF11 RX" }, \
{ name " Mux", "ADMAIF12", "ADMAIF12 RX" }, \
{ name " Mux", "ADMAIF13", "ADMAIF13 RX" }, \
{ name " Mux", "ADMAIF14", "ADMAIF14 RX" }, \
{ name " Mux", "ADMAIF15", "ADMAIF15 RX" }, \
{ name " Mux", "ADMAIF16", "ADMAIF16 RX" }, \
{ name " Mux", "ADMAIF17", "ADMAIF17 RX" }, \
{ name " Mux", "ADMAIF18", "ADMAIF18 RX" }, \
{ name " Mux", "ADMAIF19", "ADMAIF19 RX" }, \
{ name " Mux", "ADMAIF20", "ADMAIF20 RX" }, \
{ name " Mux", "I2S6", "I2S6 RX" }, \
{ name " Mux", "DMIC4", "DMIC4 RX" },
#define TEGRA210_ROUTES(name) \
TEGRA_COMMON_ROUTES(name)
#define TEGRA186_ROUTES(name) \
TEGRA_COMMON_ROUTES(name) \
TEGRA186_ONLY_ROUTES(name)
#define IN_OUT_ROUTES(name) \
{ name " RX", NULL, name " Receive" }, \
{ name " Transmit", NULL, name " TX" },
/*
* The number of entries in, and order of, this array is closely tied to the
* calculation of tegra210_ahub_codec.num_dapm_routes near the end of
* tegra210_ahub_probe()
*/
static const struct snd_soc_dapm_route tegra210_ahub_routes[] = {
TEGRA210_ROUTES("ADMAIF1")
TEGRA210_ROUTES("ADMAIF2")
TEGRA210_ROUTES("ADMAIF3")
TEGRA210_ROUTES("ADMAIF4")
TEGRA210_ROUTES("ADMAIF5")
TEGRA210_ROUTES("ADMAIF6")
TEGRA210_ROUTES("ADMAIF7")
TEGRA210_ROUTES("ADMAIF8")
TEGRA210_ROUTES("ADMAIF9")
TEGRA210_ROUTES("ADMAIF10")
TEGRA210_ROUTES("I2S1")
TEGRA210_ROUTES("I2S2")
TEGRA210_ROUTES("I2S3")
TEGRA210_ROUTES("I2S4")
TEGRA210_ROUTES("I2S5")
IN_OUT_ROUTES("DMIC1")
IN_OUT_ROUTES("DMIC2")
IN_OUT_ROUTES("DMIC3")
};
static const struct snd_soc_dapm_route tegra186_ahub_routes[] = {
TEGRA186_ROUTES("ADMAIF1")
TEGRA186_ROUTES("ADMAIF2")
TEGRA186_ROUTES("ADMAIF3")
TEGRA186_ROUTES("ADMAIF4")
TEGRA186_ROUTES("ADMAIF5")
TEGRA186_ROUTES("ADMAIF6")
TEGRA186_ROUTES("ADMAIF7")
TEGRA186_ROUTES("ADMAIF8")
TEGRA186_ROUTES("ADMAIF9")
TEGRA186_ROUTES("ADMAIF10")
TEGRA186_ROUTES("ADMAIF11")
TEGRA186_ROUTES("ADMAIF12")
TEGRA186_ROUTES("ADMAIF13")
TEGRA186_ROUTES("ADMAIF14")
TEGRA186_ROUTES("ADMAIF15")
TEGRA186_ROUTES("ADMAIF16")
TEGRA186_ROUTES("ADMAIF17")
TEGRA186_ROUTES("ADMAIF18")
TEGRA186_ROUTES("ADMAIF19")
TEGRA186_ROUTES("ADMAIF20")
TEGRA186_ROUTES("I2S1")
TEGRA186_ROUTES("I2S2")
TEGRA186_ROUTES("I2S3")
TEGRA186_ROUTES("I2S4")
TEGRA186_ROUTES("I2S5")
TEGRA186_ROUTES("I2S6")
TEGRA186_ROUTES("DSPK1")
TEGRA186_ROUTES("DSPK2")
IN_OUT_ROUTES("DMIC1")
IN_OUT_ROUTES("DMIC2")
IN_OUT_ROUTES("DMIC3")
IN_OUT_ROUTES("DMIC4")
};
static const struct snd_soc_component_driver tegra210_ahub_component = {
.dapm_widgets = tegra210_ahub_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra210_ahub_widgets),
.dapm_routes = tegra210_ahub_routes,
.num_dapm_routes = ARRAY_SIZE(tegra210_ahub_routes),
};
static const struct snd_soc_component_driver tegra186_ahub_component = {
.dapm_widgets = tegra186_ahub_widgets,
.num_dapm_widgets = ARRAY_SIZE(tegra186_ahub_widgets),
.dapm_routes = tegra186_ahub_routes,
.num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes),
};
static const struct regmap_config tegra210_ahub_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = TEGRA210_MAX_REGISTER_ADDR,
.cache_type = REGCACHE_FLAT,
};
static const struct regmap_config tegra186_ahub_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = TEGRA186_MAX_REGISTER_ADDR,
.cache_type = REGCACHE_FLAT,
};
static const struct tegra_ahub_soc_data soc_data_tegra210 = {
.cmpnt_drv = &tegra210_ahub_component,
.dai_drv = tegra210_ahub_dais,
.num_dais = ARRAY_SIZE(tegra210_ahub_dais),
.regmap_config = &tegra210_ahub_regmap_config,
.mask[0] = TEGRA210_XBAR_REG_MASK_0,
.mask[1] = TEGRA210_XBAR_REG_MASK_1,
.mask[2] = TEGRA210_XBAR_REG_MASK_2,
.mask[3] = TEGRA210_XBAR_REG_MASK_3,
.reg_count = TEGRA210_XBAR_UPDATE_MAX_REG,
};
static const struct tegra_ahub_soc_data soc_data_tegra186 = {
.cmpnt_drv = &tegra186_ahub_component,
.dai_drv = tegra186_ahub_dais,
.num_dais = ARRAY_SIZE(tegra186_ahub_dais),
.regmap_config = &tegra186_ahub_regmap_config,
.mask[0] = TEGRA186_XBAR_REG_MASK_0,
.mask[1] = TEGRA186_XBAR_REG_MASK_1,
.mask[2] = TEGRA186_XBAR_REG_MASK_2,
.mask[3] = TEGRA186_XBAR_REG_MASK_3,
.reg_count = TEGRA186_XBAR_UPDATE_MAX_REG,
};
static const struct of_device_id tegra_ahub_of_match[] = {
{ .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 },
{ .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 },
{},
};
MODULE_DEVICE_TABLE(of, tegra_ahub_of_match);
static int tegra_ahub_runtime_suspend(struct device *dev)
{
struct tegra_ahub *ahub = dev_get_drvdata(dev);
regcache_cache_only(ahub->regmap, true);
regcache_mark_dirty(ahub->regmap);
clk_disable_unprepare(ahub->clk);
return 0;
}
static int tegra_ahub_runtime_resume(struct device *dev)
{
struct tegra_ahub *ahub = dev_get_drvdata(dev);
int err;
err = clk_prepare_enable(ahub->clk);
if (err) {
dev_err(dev, "failed to enable AHUB clock, err: %d\n", err);
return err;
}
regcache_cache_only(ahub->regmap, false);
regcache_sync(ahub->regmap);
return 0;
}
static int tegra_ahub_probe(struct platform_device *pdev)
{
struct tegra_ahub *ahub;
void __iomem *regs;
int err;
ahub = devm_kzalloc(&pdev->dev, sizeof(*ahub), GFP_KERNEL);
if (!ahub)
return -ENOMEM;
ahub->soc_data = of_device_get_match_data(&pdev->dev);
platform_set_drvdata(pdev, ahub);
ahub->clk = devm_clk_get(&pdev->dev, "ahub");
if (IS_ERR(ahub->clk)) {
dev_err(&pdev->dev, "can't retrieve AHUB clock\n");
return PTR_ERR(ahub->clk);
}
regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(regs))
return PTR_ERR(regs);
ahub->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
ahub->soc_data->regmap_config);
if (IS_ERR(ahub->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(ahub->regmap);
}
regcache_cache_only(ahub->regmap, true);
err = devm_snd_soc_register_component(&pdev->dev,
ahub->soc_data->cmpnt_drv,
ahub->soc_data->dai_drv,
ahub->soc_data->num_dais);
if (err) {
dev_err(&pdev->dev, "can't register AHUB component, err: %d\n",
err);
return err;
}
err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
if (err)
return err;
pm_runtime_enable(&pdev->dev);
return 0;
}
static int tegra_ahub_remove(struct platform_device *pdev)
{
pm_runtime_disable(&pdev->dev);
return 0;
}
static const struct dev_pm_ops tegra_ahub_pm_ops = {
SET_RUNTIME_PM_OPS(tegra_ahub_runtime_suspend,
tegra_ahub_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
static struct platform_driver tegra_ahub_driver = {
.probe = tegra_ahub_probe,
.remove = tegra_ahub_remove,
.driver = {
.name = "tegra210-ahub",
.of_match_table = tegra_ahub_of_match,
.pm = &tegra_ahub_pm_ops,
},
};
module_platform_driver(tegra_ahub_driver);
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>");
MODULE_DESCRIPTION("Tegra210 ASoC AHUB driver");
MODULE_LICENSE("GPL v2");

125
sound/soc/tegra/tegra210_ahub.h Normal file
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@@ -0,0 +1,125 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* tegra210_ahub.h - TEGRA210 AHUB
*
* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
*
*/
#ifndef __TEGRA210_AHUB__H__
#define __TEGRA210_AHUB__H__
/* Tegra210 specific */
#define TEGRA210_XBAR_PART1_RX 0x200
#define TEGRA210_XBAR_PART2_RX 0x400
#define TEGRA210_XBAR_RX_STRIDE 0x4
#define TEGRA210_XBAR_AUDIO_RX_COUNT 90
#define TEGRA210_XBAR_REG_MASK_0 0xf1f03ff
#define TEGRA210_XBAR_REG_MASK_1 0x3f30031f
#define TEGRA210_XBAR_REG_MASK_2 0xff1cf313
#define TEGRA210_XBAR_REG_MASK_3 0x0
#define TEGRA210_XBAR_UPDATE_MAX_REG 3
/* Tegra186 specific */
#define TEGRA186_XBAR_PART3_RX 0x600
#define TEGRA186_XBAR_AUDIO_RX_COUNT 115
#define TEGRA186_XBAR_REG_MASK_0 0xf3fffff
#define TEGRA186_XBAR_REG_MASK_1 0x3f310f1f
#define TEGRA186_XBAR_REG_MASK_2 0xff3cf311
#define TEGRA186_XBAR_REG_MASK_3 0x3f0f00ff
#define TEGRA186_XBAR_UPDATE_MAX_REG 4
#define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG)
#define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX + \
(TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1)))
#define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX + \
(TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)))
#define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id))
#define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32)
#define DAI(sname) \
{ \
.name = #sname, \
.playback = { \
.stream_name = #sname " Receive", \
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
.capture = { \
.stream_name = #sname " Transmit", \
.channels_min = 1, \
.channels_max = 16, \
.rates = SNDRV_PCM_RATE_8000_192000, \
.formats = SNDRV_PCM_FMTBIT_S8 | \
SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S32_LE, \
}, \
}
#define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues) \
{ \
.reg = xreg, \
.shift_l = shift, \
.shift_r = shift, \
.items = xmax, \
.texts = xtexts, \
.values = xvalues, \
.mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0 \
}
#define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, xtexts, xvalues) \
static struct soc_enum name = \
SOC_VALUE_ENUM_WIDE(xreg, shift, ARRAY_SIZE(xtexts), \
xtexts, xvalues)
#define MUX_ENUM_CTRL_DECL(ename, id) \
SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
tegra210_ahub_mux_texts, \
tegra210_ahub_mux_values); \
static const struct snd_kcontrol_new ename##_control = \
SOC_DAPM_ENUM_EXT("Route", ename##_enum, \
tegra_ahub_get_value_enum, \
tegra_ahub_put_value_enum)
#define MUX_ENUM_CTRL_DECL_186(ename, id) \
SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
tegra186_ahub_mux_texts, \
tegra186_ahub_mux_values); \
static const struct snd_kcontrol_new ename##_control = \
SOC_DAPM_ENUM_EXT("Route", ename##_enum, \
tegra_ahub_get_value_enum, \
tegra_ahub_put_value_enum)
#define WIDGETS(sname, ename) \
SND_SOC_DAPM_AIF_IN(sname " RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
SND_SOC_DAPM_AIF_OUT(sname " TX", NULL, 0, SND_SOC_NOPM, 0, 0), \
SND_SOC_DAPM_MUX(sname " Mux", SND_SOC_NOPM, 0, 0, \
&ename##_control)
#define TX_WIDGETS(sname) \
SND_SOC_DAPM_AIF_IN(sname " RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
SND_SOC_DAPM_AIF_OUT(sname " TX", NULL, 0, SND_SOC_NOPM, 0, 0)
struct tegra_ahub_soc_data {
const struct regmap_config *regmap_config;
const struct snd_soc_component_driver *cmpnt_drv;
struct snd_soc_dai_driver *dai_drv;
unsigned int mask[4];
unsigned int reg_count;
unsigned int num_dais;
};
struct tegra_ahub {
const struct tegra_ahub_soc_data *soc_data;
struct regmap *regmap;
struct clk *clk;
};
#endif

527
sound/soc/tegra/tegra210_dmic.c
View File

@@ -1,70 +1,43 @@
// SPDX-License-Identifier: GPL-2.0-only
/* /*
* tegra210_dmic_alt.c - Tegra210 DMIC driver * tegra210_dmic.c - Tegra210 DMIC driver
* *
* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/device.h> #include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/of.h> #include <linux/of_device.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <soc/tegra/chip-id.h>
#include <sound/core.h> #include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h> #include <sound/pcm_params.h>
#include <sound/soc.h> #include <sound/soc.h>
#include <linux/of_device.h> #include "tegra210_dmic.h"
#include <linux/pinctrl/pinconf-tegra.h> #include "tegra_cif.h"
#include "tegra210_xbar_alt.h"
#include "tegra210_dmic_alt.h"
#include "ahub_unit_fpga_clock.h"
#define DRV_NAME "tegra210-dmic"
static const struct reg_default tegra210_dmic_reg_defaults[] = { static const struct reg_default tegra210_dmic_reg_defaults[] = {
{ TEGRA210_DMIC_TX_INT_MASK, 0x00000001}, { TEGRA210_DMIC_TX_INT_MASK, 0x00000001 },
{ TEGRA210_DMIC_TX_CIF_CTRL, 0x00007700}, { TEGRA210_DMIC_TX_CIF_CTRL, 0x00007700 },
{ TEGRA210_DMIC_CG, 0x1}, { TEGRA210_DMIC_CG, 0x1 },
{ TEGRA210_DMIC_CTRL, 0x00000301}, { TEGRA210_DMIC_CTRL, 0x00000301 },
{ TEGRA210_DMIC_DCR_FILTER_GAIN, 0x00800000}, /* Below enables all filters - DCR, LP and SC */
{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_0, 0x00800000}, { TEGRA210_DMIC_DBG_CTRL, 0xe },
{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_1, 0xff800000}, /* Below as per latest POR value */
{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_3, 0xff800347}, { TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4, 0x0 },
{ TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4, 0xffc0ff97}, /* LP filter is configured for pass through and used to apply gain */
{ TEGRA210_DMIC_LP_FILTER_GAIN, 0x004c255a}, { TEGRA210_DMIC_LP_BIQUAD_0_COEF_0, 0x00800000 },
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_0, 0x00800000}, { TEGRA210_DMIC_LP_BIQUAD_0_COEF_1, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_1, 0x00ffa74b}, { TEGRA210_DMIC_LP_BIQUAD_0_COEF_2, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_2, 0x00800000}, { TEGRA210_DMIC_LP_BIQUAD_0_COEF_3, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_3, 0x009e382a}, { TEGRA210_DMIC_LP_BIQUAD_0_COEF_4, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_0_COEF_4, 0x00380f38}, { TEGRA210_DMIC_LP_BIQUAD_1_COEF_0, 0x00800000 },
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_0, 0x00800000}, { TEGRA210_DMIC_LP_BIQUAD_1_COEF_1, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_1, 0x00fe1178}, { TEGRA210_DMIC_LP_BIQUAD_1_COEF_2, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_2, 0x00800000}, { TEGRA210_DMIC_LP_BIQUAD_1_COEF_3, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_3, 0x00e05f02}, { TEGRA210_DMIC_LP_BIQUAD_1_COEF_4, 0x0 },
{ TEGRA210_DMIC_LP_BIQUAD_1_COEF_4, 0x006fc80d},
{ TEGRA210_DMIC_CORRECTION_FILTER_GAIN, 0x010628f6},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_0, 0x00800000},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_3, 0x0067ffff},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_0, 0x00800000},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_1, 0x0048f5c2},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_3, 0x00562394},
{ TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_4, 0x00169446},
}; };
static int tegra210_dmic_runtime_suspend(struct device *dev) static int tegra210_dmic_runtime_suspend(struct device *dev)
@@ -74,8 +47,7 @@ static int tegra210_dmic_runtime_suspend(struct device *dev)
regcache_cache_only(dmic->regmap, true); regcache_cache_only(dmic->regmap, true);
regcache_mark_dirty(dmic->regmap); regcache_mark_dirty(dmic->regmap);
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) clk_disable_unprepare(dmic->clk_dmic);
clk_disable_unprepare(dmic->clk_dmic);
return 0; return 0;
} }
@@ -83,14 +55,12 @@ static int tegra210_dmic_runtime_suspend(struct device *dev)
static int tegra210_dmic_runtime_resume(struct device *dev) static int tegra210_dmic_runtime_resume(struct device *dev)
{ {
struct tegra210_dmic *dmic = dev_get_drvdata(dev); struct tegra210_dmic *dmic = dev_get_drvdata(dev);
int ret; int err;
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) { err = clk_prepare_enable(dmic->clk_dmic);
ret = clk_prepare_enable(dmic->clk_dmic); if (err) {
if (ret) { dev_err(dev, "failed to enable DMIC clock, err: %d\n", err);
dev_err(dev, "clk_enable failed: %d\n", ret); return err;
return ret;
}
} }
regcache_cache_only(dmic->regmap, false); regcache_cache_only(dmic->regmap, false);
@@ -99,221 +69,176 @@ static int tegra210_dmic_runtime_resume(struct device *dev)
return 0; return 0;
} }
static const int tegra210_dmic_fmt_values[] = { static const unsigned int tegra210_dmic_fmts[] = {
0, 0,
TEGRA210_AUDIOCIF_BITS_16, TEGRA_ACIF_BITS_16,
TEGRA210_AUDIOCIF_BITS_32, TEGRA_ACIF_BITS_32,
}; };
static int tegra210_dmic_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct device *dev = dai->dev;
struct tegra210_dmic *dmic = snd_soc_dai_get_drvdata(dai);
int ret;
if (dmic->prod_name != NULL) {
ret = tegra_pinctrl_config_prod(dev, dmic->prod_name);
if (ret < 0) {
dev_warn(dev, "Failed to set %s setting\n",
dmic->prod_name);
}
}
return 0;
}
static int tegra210_dmic_hw_params(struct snd_pcm_substream *substream, static int tegra210_dmic_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai) struct snd_soc_dai *dai)
{ {
struct device *dev = dai->dev;
struct tegra210_dmic *dmic = snd_soc_dai_get_drvdata(dai); struct tegra210_dmic *dmic = snd_soc_dai_get_drvdata(dai);
int srate, dmic_clk, osr = dmic->osr_val, ret; unsigned int srate, clk_rate, channels;
struct tegra210_xbar_cif_conf cif_conf; struct tegra_cif_conf cif_conf;
unsigned long long boost_gain; unsigned long long gain_q23 = DEFAULT_GAIN_Q23;
unsigned int channels; int err;
memset(&cif_conf, 0, sizeof(struct tegra210_xbar_cif_conf)); memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
srate = params_rate(params);
if (dmic->sample_rate_via_control)
srate = dmic->sample_rate_via_control;
dmic_clk = (1 << (6+osr)) * srate;
channels = params_channels(params); channels = params_channels(params);
if (dmic->channels_via_control)
channels = dmic->channels_via_control; cif_conf.audio_ch = channels;
cif_conf.audio_channels = channels; if (dmic->audio_ch_override)
cif_conf.audio_ch = dmic->audio_ch_override;
switch (dmic->ch_select) { switch (dmic->ch_select) {
case DMIC_CH_SELECT_LEFT: case DMIC_CH_SELECT_LEFT:
case DMIC_CH_SELECT_RIGHT: case DMIC_CH_SELECT_RIGHT:
cif_conf.client_channels = 1; cif_conf.client_ch = 1;
break; break;
case DMIC_CH_SELECT_STEREO: case DMIC_CH_SELECT_STEREO:
cif_conf.client_channels = 2; cif_conf.client_ch = 2;
break; break;
default: default:
dev_err(dev, "unsupported ch_select value\n"); dev_err(dai->dev, "invalid DMIC client channels\n");
return -EINVAL; return -EINVAL;
} }
if ((tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) { srate = params_rate(params);
program_dmic_gpio(); if (dmic->srate_override)
program_dmic_clk(dmic_clk); srate = dmic->srate_override;
} else {
ret = clk_set_rate(dmic->clk_dmic, dmic_clk); /*
if (ret) { * DMIC clock rate is a multiple of 'Over Sampling Ratio' and
dev_err(dev, "Can't set dmic clock rate: %d\n", ret); * 'Sample Rate'. The supported OSR values are 64, 128 and 256.
return ret; */
} clk_rate = (DMIC_OSR_FACTOR << dmic->osr_val) * srate;
err = clk_set_rate(dmic->clk_dmic, clk_rate);
if (err) {
dev_err(dai->dev, "can't set DMIC clock rate %u, err: %d\n",
clk_rate, err);
return err;
} }
regmap_update_bits(dmic->regmap, TEGRA210_DMIC_CTRL, regmap_update_bits(dmic->regmap,
TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK, /* Reg */
dmic->lrsel << LRSEL_POL_SHIFT); TEGRA210_DMIC_CTRL,
regmap_update_bits(dmic->regmap, TEGRA210_DMIC_CTRL, /* Mask */
TEGRA210_DMIC_CTRL_OSR_MASK, osr << OSR_SHIFT); TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK |
regmap_update_bits(dmic->regmap, TEGRA210_DMIC_DBG_CTRL, TEGRA210_DMIC_CTRL_OSR_MASK |
TEGRA210_DMIC_DBG_CTRL_SC_ENABLE,
TEGRA210_DMIC_DBG_CTRL_SC_ENABLE);
regmap_update_bits(dmic->regmap, TEGRA210_DMIC_DBG_CTRL,
TEGRA210_DMIC_DBG_CTRL_DCR_ENABLE,
TEGRA210_DMIC_DBG_CTRL_DCR_ENABLE);
regmap_update_bits(dmic->regmap, TEGRA210_DMIC_CTRL,
TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK, TEGRA210_DMIC_CTRL_CHANNEL_SELECT_MASK,
(dmic->ch_select + 1) << CH_SEL_SHIFT); /* Value */
(dmic->lrsel << LRSEL_POL_SHIFT) |
(dmic->osr_val << OSR_SHIFT) |
((dmic->ch_select + 1) << CH_SEL_SHIFT));
/*
* Use LP filter gain register to apply boost.
* Boost Gain control has 100x factor.
*/
if (dmic->boost_gain)
gain_q23 = (gain_q23 * dmic->boost_gain) / 100;
/* Configure LPF for passthrough and use */
/* its gain register for applying boost; */
/* Boost Gain control has 100x factor */
boost_gain = 0x00800000;
if (dmic->boost_gain > 0) {
boost_gain = ((boost_gain * dmic->boost_gain) / 100);
if (boost_gain > 0x7FFFFFFF) {
dev_warn(dev, "Boost Gain overflow\n");
boost_gain = 0x7FFFFFFF;
}
}
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_FILTER_GAIN, regmap_write(dmic->regmap, TEGRA210_DMIC_LP_FILTER_GAIN,
(unsigned int)boost_gain); (unsigned int)gain_q23);
regmap_update_bits(dmic->regmap, TEGRA210_DMIC_DBG_CTRL,
TEGRA210_DMIC_DBG_CTRL_LP_ENABLE,
TEGRA210_DMIC_DBG_CTRL_LP_ENABLE);
/* Configure the two biquads for passthrough, */
/* i.e. b0=1, b1=0, b2=0, a1=0, a2=0 */
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_BIQUAD_0_COEF_0,
0x00800000);
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_BIQUAD_0_COEF_1,
0x00000000);
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_BIQUAD_0_COEF_2,
0x00000000);
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_BIQUAD_0_COEF_3,
0x00000000);
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_BIQUAD_0_COEF_4,
0x00000000);
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_BIQUAD_1_COEF_0,
0x00800000);
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_BIQUAD_1_COEF_1,
0x00000000);
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_BIQUAD_1_COEF_2,
0x00000000);
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_BIQUAD_1_COEF_3,
0x00000000);
regmap_write(dmic->regmap, TEGRA210_DMIC_LP_BIQUAD_1_COEF_4,
0x00000000);
switch (params_format(params)) { switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE: case SNDRV_PCM_FORMAT_S16_LE:
cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_16; cif_conf.audio_bits = TEGRA_ACIF_BITS_16;
break; break;
case SNDRV_PCM_FORMAT_S32_LE: case SNDRV_PCM_FORMAT_S32_LE:
cif_conf.audio_bits = TEGRA210_AUDIOCIF_BITS_32; cif_conf.audio_bits = TEGRA_ACIF_BITS_32;
break; break;
default: default:
dev_err(dev, "Wrong format!\n"); dev_err(dai->dev, "unsupported format!\n");
return -EINVAL; return -ENOTSUPP;
} }
if (dmic->format_out) if (dmic->audio_bits_override)
cif_conf.audio_bits = tegra210_dmic_fmt_values[dmic->format_out]; cif_conf.audio_bits =
cif_conf.client_bits = TEGRA210_AUDIOCIF_BITS_24; tegra210_dmic_fmts[dmic->audio_bits_override];
cif_conf.client_bits = TEGRA_ACIF_BITS_24;
cif_conf.mono_conv = dmic->mono_to_stereo; cif_conf.mono_conv = dmic->mono_to_stereo;
cif_conf.stereo_conv = dmic->stereo_to_mono; cif_conf.stereo_conv = dmic->stereo_to_mono;
tegra210_xbar_set_cif(dmic->regmap, TEGRA210_DMIC_TX_CIF_CTRL, tegra_set_cif(dmic->regmap, TEGRA210_DMIC_TX_CIF_CTRL, &cif_conf);
&cif_conf);
return 0; return 0;
} }
static int tegra210_dmic_get_control(struct snd_kcontrol *kcontrol, static int tegra210_dmic_get_control(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol) struct snd_ctl_elem_value *ucontrol)
{ {
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_codec_get_drvdata(codec); struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
if (strstr(kcontrol->id.name, "Boost")) if (strstr(kcontrol->id.name, "Boost Gain"))
ucontrol->value.integer.value[0] = dmic->boost_gain; ucontrol->value.integer.value[0] = dmic->boost_gain;
else if (strstr(kcontrol->id.name, "Controller Channel Select")) else if (strstr(kcontrol->id.name, "Channel Select"))
ucontrol->value.integer.value[0] = dmic->ch_select; ucontrol->value.integer.value[0] = dmic->ch_select;
else if (strstr(kcontrol->id.name, "Capture mono to stereo")) else if (strstr(kcontrol->id.name, "Mono To Stereo"))
ucontrol->value.integer.value[0] = dmic->mono_to_stereo; ucontrol->value.integer.value[0] = dmic->mono_to_stereo;
else if (strstr(kcontrol->id.name, "Capture stereo to mono")) else if (strstr(kcontrol->id.name, "Stereo To Mono"))
ucontrol->value.integer.value[0] = dmic->stereo_to_mono; ucontrol->value.integer.value[0] = dmic->stereo_to_mono;
else if (strstr(kcontrol->id.name, "output bit format")) else if (strstr(kcontrol->id.name, "Audio Bit Format"))
ucontrol->value.integer.value[0] = dmic->format_out; ucontrol->value.integer.value[0] = dmic->audio_bits_override;
else if (strstr(kcontrol->id.name, "Sample Rate")) else if (strstr(kcontrol->id.name, "Sample Rate"))
ucontrol->value.integer.value[0] = ucontrol->value.integer.value[0] = dmic->srate_override;
dmic->sample_rate_via_control; else if (strstr(kcontrol->id.name, "Audio Channels"))
else if (strstr(kcontrol->id.name, "Channels")) ucontrol->value.integer.value[0] = dmic->audio_ch_override;
ucontrol->value.integer.value[0] =
dmic->channels_via_control;
else if (strstr(kcontrol->id.name, "OSR Value")) else if (strstr(kcontrol->id.name, "OSR Value"))
ucontrol->value.integer.value[0] = dmic->osr_val; ucontrol->value.integer.value[0] = dmic->osr_val;
else if (strstr(kcontrol->id.name, "LR Select")) else if (strstr(kcontrol->id.name, "LR Polarity Select"))
ucontrol->value.integer.value[0] = dmic->lrsel; ucontrol->value.integer.value[0] = dmic->lrsel;
return 0; return 0;
} }
static int tegra210_dmic_put_control(struct snd_kcontrol *kcontrol, static int tegra210_dmic_put_control(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol) struct snd_ctl_elem_value *ucontrol)
{ {
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
struct tegra210_dmic *dmic = snd_soc_codec_get_drvdata(codec); struct tegra210_dmic *dmic = snd_soc_component_get_drvdata(comp);
int value = ucontrol->value.integer.value[0]; int value = ucontrol->value.integer.value[0];
if (strstr(kcontrol->id.name, "Boost")) if (strstr(kcontrol->id.name, "Boost Gain"))
dmic->boost_gain = value; dmic->boost_gain = value;
else if (strstr(kcontrol->id.name, "Controller Channel Select")) else if (strstr(kcontrol->id.name, "Channel Select"))
dmic->ch_select = ucontrol->value.integer.value[0]; dmic->ch_select = ucontrol->value.integer.value[0];
else if (strstr(kcontrol->id.name, "Capture mono to stereo")) else if (strstr(kcontrol->id.name, "Mono To Stereo"))
dmic->mono_to_stereo = value; dmic->mono_to_stereo = value;
else if (strstr(kcontrol->id.name, "Capture stereo to mono")) else if (strstr(kcontrol->id.name, "Stereo To Mono"))
dmic->stereo_to_mono = value; dmic->stereo_to_mono = value;
else if (strstr(kcontrol->id.name, "output bit format")) else if (strstr(kcontrol->id.name, "Audio Bit Format"))
dmic->format_out = value; dmic->audio_bits_override = value;
else if (strstr(kcontrol->id.name, "Sample Rate")) else if (strstr(kcontrol->id.name, "Sample Rate"))
dmic->sample_rate_via_control = value; dmic->srate_override = value;
else if (strstr(kcontrol->id.name, "Channels")) else if (strstr(kcontrol->id.name, "Audio Channels"))
dmic->channels_via_control = value; dmic->audio_ch_override = value;
else if (strstr(kcontrol->id.name, "OSR Value")) else if (strstr(kcontrol->id.name, "OSR Value"))
dmic->osr_val = value; dmic->osr_val = value;
else if (strstr(kcontrol->id.name, "LR Select")) else if (strstr(kcontrol->id.name, "LR Polarity Select"))
dmic->lrsel = value; dmic->lrsel = value;
return 0; return 0;
} }
static struct snd_soc_dai_ops tegra210_dmic_dai_ops = { static const struct snd_soc_dai_ops tegra210_dmic_dai_ops = {
.hw_params = tegra210_dmic_hw_params, .hw_params = tegra210_dmic_hw_params,
.startup = tegra210_dmic_startup,
}; };
/*
* Three DAIs are exposed
* 1. "CIF" DAI for connecting with XBAR
* 2. "DAP" DAI for connecting with CODEC
* 3. "DUMMY_SOURCE" can be used when no external
* codec connection is available. In such case
* "DAP" is connected with "DUMMY_SOURCE"
*/
static struct snd_soc_dai_driver tegra210_dmic_dais[] = { static struct snd_soc_dai_driver tegra210_dmic_dais[] = {
{ {
.name = "CIF", .name = "CIF",
@@ -322,7 +247,8 @@ static struct snd_soc_dai_driver tegra210_dmic_dais[] = {
.channels_min = 1, .channels_min = 1,
.channels_max = 2, .channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000, .rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE, .formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
}, },
.ops = &tegra210_dmic_dai_ops, .ops = &tegra210_dmic_dai_ops,
.symmetric_rates = 1, .symmetric_rates = 1,
@@ -334,10 +260,9 @@ static struct snd_soc_dai_driver tegra210_dmic_dais[] = {
.channels_min = 1, .channels_min = 1,
.channels_max = 2, .channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000, .rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE, .formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
}, },
.ops = &tegra210_dmic_dai_ops,
.symmetric_rates = 1,
}, },
{ {
.name = "DUMMY_SOURCE", .name = "DUMMY_SOURCE",
@@ -346,32 +271,29 @@ static struct snd_soc_dai_driver tegra210_dmic_dais[] = {
.channels_min = 1, .channels_min = 1,
.channels_max = 2, .channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000, .rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE, .formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S32_LE,
}, },
} }
}; };
static const struct snd_soc_dapm_widget tegra210_dmic_widgets[] = { static const struct snd_soc_dapm_widget tegra210_dmic_widgets[] = {
SND_SOC_DAPM_AIF_OUT("DMIC TX", NULL, 0, SND_SOC_NOPM, SND_SOC_DAPM_AIF_IN("DMIC TX", NULL, 0, TEGRA210_DMIC_ENABLE, 0, 0),
0, 0),
SND_SOC_DAPM_AIF_IN("DMIC RX", NULL, 0, TEGRA210_DMIC_ENABLE,
0, 0),
SND_SOC_DAPM_MIC("Dummy Input", NULL), SND_SOC_DAPM_MIC("Dummy Input", NULL),
}; };
static const struct snd_soc_dapm_route tegra210_dmic_routes[] = { static const struct snd_soc_dapm_route tegra210_dmic_routes[] = {
{ "DMIC RX", NULL, "DMIC Receive" }, { "DMIC TX", NULL, "DMIC Receive" },
{ "DMIC TX", NULL, "DMIC RX" },
{ "DMIC Transmit", NULL, "DMIC TX" }, { "DMIC Transmit", NULL, "DMIC TX" },
{ "Dummy Capture", NULL, "Dummy Input" }, { "Dummy Capture", NULL, "Dummy Input" },
}; };
static const char * const tegra210_dmic_ch_select[] = { static const char * const tegra210_dmic_ch_select[] = {
"L", "R", "Stereo", "Left", "Right", "Stereo",
}; };
static const struct soc_enum tegra210_dmic_ch_enum = static const struct soc_enum tegra210_dmic_ch_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra210_dmic_ch_select), SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_ch_select),
tegra210_dmic_ch_select); tegra210_dmic_ch_select);
static const char * const tegra210_dmic_mono_conv_text[] = { static const char * const tegra210_dmic_mono_conv_text[] = {
@@ -383,13 +305,11 @@ static const char * const tegra210_dmic_stereo_conv_text[] = {
}; };
static const struct soc_enum tegra210_dmic_mono_conv_enum = static const struct soc_enum tegra210_dmic_mono_conv_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_mono_conv_text),
ARRAY_SIZE(tegra210_dmic_mono_conv_text),
tegra210_dmic_mono_conv_text); tegra210_dmic_mono_conv_text);
static const struct soc_enum tegra210_dmic_stereo_conv_enum = static const struct soc_enum tegra210_dmic_stereo_conv_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_stereo_conv_text),
ARRAY_SIZE(tegra210_dmic_stereo_conv_text),
tegra210_dmic_stereo_conv_text); tegra210_dmic_stereo_conv_text);
static const char * const tegra210_dmic_format_text[] = { static const char * const tegra210_dmic_format_text[] = {
@@ -399,7 +319,7 @@ static const char * const tegra210_dmic_format_text[] = {
}; };
static const struct soc_enum tegra210_dmic_format_enum = static const struct soc_enum tegra210_dmic_format_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra210_dmic_format_text), SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_format_text),
tegra210_dmic_format_text); tegra210_dmic_format_text);
static const char * const tegra210_dmic_osr_text[] = { static const char * const tegra210_dmic_osr_text[] = {
@@ -407,7 +327,7 @@ static const char * const tegra210_dmic_osr_text[] = {
}; };
static const struct soc_enum tegra210_dmic_osr_enum = static const struct soc_enum tegra210_dmic_osr_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra210_dmic_osr_text), SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_osr_text),
tegra210_dmic_osr_text); tegra210_dmic_osr_text);
static const char * const tegra210_dmic_lrsel_text[] = { static const char * const tegra210_dmic_lrsel_text[] = {
@@ -415,88 +335,68 @@ static const char * const tegra210_dmic_lrsel_text[] = {
}; };
static const struct soc_enum tegra210_dmic_lrsel_enum = static const struct soc_enum tegra210_dmic_lrsel_enum =
SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tegra210_dmic_lrsel_text), SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(tegra210_dmic_lrsel_text),
tegra210_dmic_lrsel_text); tegra210_dmic_lrsel_text);
static const struct snd_kcontrol_new tegra210_dmic_controls[] = { static const struct snd_kcontrol_new tegra210_dmic_controls[] = {
SOC_SINGLE_EXT("Boost Gain", 0, 0, 25599, 0, tegra210_dmic_get_control, SOC_SINGLE_EXT("Boost Gain", 0, 0, MAX_BOOST_GAIN, 0,
tegra210_dmic_put_control), tegra210_dmic_get_control, tegra210_dmic_put_control),
SOC_ENUM_EXT("Controller Channel Select", tegra210_dmic_ch_enum, SOC_ENUM_EXT("Channel Select", tegra210_dmic_ch_enum,
tegra210_dmic_get_control, tegra210_dmic_put_control), tegra210_dmic_get_control, tegra210_dmic_put_control),
SOC_ENUM_EXT("Capture mono to stereo conv", SOC_ENUM_EXT("Mono To Stereo",
tegra210_dmic_mono_conv_enum, tegra210_dmic_get_control, tegra210_dmic_mono_conv_enum, tegra210_dmic_get_control,
tegra210_dmic_put_control), tegra210_dmic_put_control),
SOC_ENUM_EXT("Capture stereo to mono conv", SOC_ENUM_EXT("Stereo To Mono",
tegra210_dmic_stereo_conv_enum, tegra210_dmic_get_control, tegra210_dmic_stereo_conv_enum, tegra210_dmic_get_control,
tegra210_dmic_put_control), tegra210_dmic_put_control),
SOC_ENUM_EXT("output bit format", tegra210_dmic_format_enum, SOC_ENUM_EXT("Audio Bit Format", tegra210_dmic_format_enum,
tegra210_dmic_get_control, tegra210_dmic_put_control), tegra210_dmic_get_control, tegra210_dmic_put_control),
SOC_SINGLE_EXT("Sample Rate", 0, 0, 48000, 0, tegra210_dmic_get_control, SOC_SINGLE_EXT("Sample Rate", 0, 0, 48000, 0, tegra210_dmic_get_control,
tegra210_dmic_put_control), tegra210_dmic_put_control),
SOC_SINGLE_EXT("Channels", 0, 0, 2, 0, tegra210_dmic_get_control, SOC_SINGLE_EXT("Audio Channels", 0, 0, 2, 0, tegra210_dmic_get_control,
tegra210_dmic_put_control), tegra210_dmic_put_control),
SOC_ENUM_EXT("OSR Value", tegra210_dmic_osr_enum, SOC_ENUM_EXT("OSR Value", tegra210_dmic_osr_enum,
tegra210_dmic_get_control, tegra210_dmic_put_control), tegra210_dmic_get_control, tegra210_dmic_put_control),
SOC_ENUM_EXT("LR Select", tegra210_dmic_lrsel_enum, SOC_ENUM_EXT("LR Polarity Select", tegra210_dmic_lrsel_enum,
tegra210_dmic_get_control, tegra210_dmic_put_control), tegra210_dmic_get_control, tegra210_dmic_put_control),
}; };
static struct snd_soc_codec_driver tegra210_dmic_codec = { static const struct snd_soc_component_driver tegra210_dmic_compnt = {
.idle_bias_off = 1, .dapm_widgets = tegra210_dmic_widgets,
.component_driver = { .num_dapm_widgets = ARRAY_SIZE(tegra210_dmic_widgets),
.dapm_widgets = tegra210_dmic_widgets, .dapm_routes = tegra210_dmic_routes,
.num_dapm_widgets = ARRAY_SIZE(tegra210_dmic_widgets), .num_dapm_routes = ARRAY_SIZE(tegra210_dmic_routes),
.dapm_routes = tegra210_dmic_routes, .controls = tegra210_dmic_controls,
.num_dapm_routes = ARRAY_SIZE(tegra210_dmic_routes), .num_controls = ARRAY_SIZE(tegra210_dmic_controls),
.controls = tegra210_dmic_controls,
.num_controls = ARRAY_SIZE(tegra210_dmic_controls),
},
}; };
/* Regmap callback functions */
static bool tegra210_dmic_wr_reg(struct device *dev, unsigned int reg) static bool tegra210_dmic_wr_reg(struct device *dev, unsigned int reg)
{ {
switch (reg) { switch (reg) {
case TEGRA210_DMIC_TX_INT_MASK: case TEGRA210_DMIC_TX_INT_MASK ... TEGRA210_DMIC_TX_CIF_CTRL:
case TEGRA210_DMIC_TX_INT_SET: case TEGRA210_DMIC_ENABLE ... TEGRA210_DMIC_CG:
case TEGRA210_DMIC_TX_INT_CLEAR:
case TEGRA210_DMIC_TX_CIF_CTRL:
case TEGRA210_DMIC_ENABLE:
case TEGRA210_DMIC_SOFT_RESET:
case TEGRA210_DMIC_CG:
case TEGRA210_DMIC_CTRL: case TEGRA210_DMIC_CTRL:
case TEGRA210_DMIC_DBG_CTRL:
case TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4 ... TEGRA210_DMIC_LP_BIQUAD_1_COEF_4:
return true; return true;
default: default:
if (((reg % 4) == 0) && (reg >= TEGRA210_DMIC_DBG_CTRL) && return false;
(reg <= TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_4))
return true;
else
return false;
}; };
} }
static bool tegra210_dmic_rd_reg(struct device *dev, unsigned int reg) static bool tegra210_dmic_rd_reg(struct device *dev, unsigned int reg)
{ {
if (tegra210_dmic_wr_reg(dev, reg))
return true;
switch (reg) { switch (reg) {
case TEGRA210_DMIC_TX_STATUS: case TEGRA210_DMIC_TX_STATUS:
case TEGRA210_DMIC_TX_INT_STATUS: case TEGRA210_DMIC_TX_INT_STATUS:
case TEGRA210_DMIC_TX_INT_MASK:
case TEGRA210_DMIC_TX_INT_SET:
case TEGRA210_DMIC_TX_INT_CLEAR:
case TEGRA210_DMIC_TX_CIF_CTRL:
case TEGRA210_DMIC_ENABLE:
case TEGRA210_DMIC_SOFT_RESET:
case TEGRA210_DMIC_CG:
case TEGRA210_DMIC_STATUS: case TEGRA210_DMIC_STATUS:
case TEGRA210_DMIC_INT_STATUS: case TEGRA210_DMIC_INT_STATUS:
case TEGRA210_DMIC_CTRL:
return true; return true;
default: default:
if (((reg % 4) == 0) && (reg >= TEGRA210_DMIC_DBG_CTRL) && return false;
(reg <= TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_4))
return true;
else
return false;
}; };
} }
@@ -519,11 +419,10 @@ static const struct regmap_config tegra210_dmic_regmap_config = {
.reg_bits = 32, .reg_bits = 32,
.reg_stride = 4, .reg_stride = 4,
.val_bits = 32, .val_bits = 32,
.max_register = TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_4, .max_register = TEGRA210_DMIC_LP_BIQUAD_1_COEF_4,
.writeable_reg = tegra210_dmic_wr_reg, .writeable_reg = tegra210_dmic_wr_reg,
.readable_reg = tegra210_dmic_rd_reg, .readable_reg = tegra210_dmic_rd_reg,
.volatile_reg = tegra210_dmic_volatile_reg, .volatile_reg = tegra210_dmic_volatile_reg,
.precious_reg = NULL,
.reg_defaults = tegra210_dmic_reg_defaults, .reg_defaults = tegra210_dmic_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tegra210_dmic_reg_defaults), .num_reg_defaults = ARRAY_SIZE(tegra210_dmic_reg_defaults),
.cache_type = REGCACHE_FLAT, .cache_type = REGCACHE_FLAT,
@@ -533,85 +432,62 @@ static const struct of_device_id tegra210_dmic_of_match[] = {
{ .compatible = "nvidia,tegra210-dmic" }, { .compatible = "nvidia,tegra210-dmic" },
{}, {},
}; };
MODULE_DEVICE_TABLE(of, tegra210_dmic_of_match);
static int tegra210_dmic_platform_probe(struct platform_device *pdev) static int tegra210_dmic_probe(struct platform_device *pdev)
{ {
struct device *dev = &pdev->dev;
struct tegra210_dmic *dmic; struct tegra210_dmic *dmic;
struct device_node *np = pdev->dev.of_node;
struct resource *mem;
void __iomem *regs; void __iomem *regs;
int ret = 0; int err;
const struct of_device_id *match;
match = of_match_device(tegra210_dmic_of_match, &pdev->dev); dmic = devm_kzalloc(dev, sizeof(*dmic), GFP_KERNEL);
if (!match) {
dev_err(&pdev->dev, "Error: No device match found\n");
return -ENODEV;
}
dmic = devm_kzalloc(&pdev->dev, sizeof(*dmic), GFP_KERNEL);
if (!dmic) if (!dmic)
return -ENOMEM; return -ENOMEM;
dmic->prod_name = NULL;
dmic->osr_val = DMIC_OSR_64; dmic->osr_val = DMIC_OSR_64;
dmic->ch_select = DMIC_CH_SELECT_STEREO; dmic->ch_select = DMIC_CH_SELECT_STEREO;
dev_set_drvdata(&pdev->dev, dmic); dmic->lrsel = DMIC_LRSEL_LEFT;
dmic->boost_gain = 0;
dmic->stereo_to_mono = 0; /* "CH0" */
if (!(tegra_platform_is_unit_fpga() || tegra_platform_is_fpga())) { dev_set_drvdata(dev, dmic);
dmic->clk_dmic = devm_clk_get(&pdev->dev, "dmic");
if (IS_ERR(dmic->clk_dmic)) { dmic->clk_dmic = devm_clk_get(dev, "dmic");
dev_err(&pdev->dev, "Can't retrieve dmic clock\n"); if (IS_ERR(dmic->clk_dmic)) {
return PTR_ERR(dmic->clk_dmic); dev_err(dev, "can't retrieve DMIC clock\n");
} return PTR_ERR(dmic->clk_dmic);
} }
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); regs = devm_platform_ioremap_resource(pdev, 0);
regs = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(regs)) if (IS_ERR(regs))
return PTR_ERR(regs); return PTR_ERR(regs);
dmic->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
dmic->regmap = devm_regmap_init_mmio(dev, regs,
&tegra210_dmic_regmap_config); &tegra210_dmic_regmap_config);
if (IS_ERR(dmic->regmap)) { if (IS_ERR(dmic->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n"); dev_err(dev, "regmap init failed\n");
return PTR_ERR(dmic->regmap); return PTR_ERR(dmic->regmap);
} }
regcache_cache_only(dmic->regmap, true); regcache_cache_only(dmic->regmap, true);
/* Below patch is as per latest POR value */ err = devm_snd_soc_register_component(dev, &tegra210_dmic_compnt,
regmap_write(dmic->regmap, TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4, tegra210_dmic_dais,
0x00000000); ARRAY_SIZE(tegra210_dmic_dais));
if (err) {
pm_runtime_enable(&pdev->dev); dev_err(dev, "can't register DMIC component, err: %d\n", err);
ret = snd_soc_register_codec(&pdev->dev, &tegra210_dmic_codec, return err;
tegra210_dmic_dais,
ARRAY_SIZE(tegra210_dmic_dais));
if (ret != 0) {
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
pm_runtime_disable(&pdev->dev);
return ret;
} }
if (of_property_read_string(np, "prod-name", &dmic->prod_name) == 0) { pm_runtime_enable(dev);
ret = tegra_pinctrl_config_prod(&pdev->dev, dmic->prod_name);
if (ret < 0)
dev_warn(&pdev->dev, "Failed to set %s setting\n",
dmic->prod_name);
}
return 0; return 0;
} }
static int tegra210_dmic_platform_remove(struct platform_device *pdev) static int tegra210_dmic_remove(struct platform_device *pdev)
{ {
struct tegra210_dmic *dmic;
dmic = dev_get_drvdata(&pdev->dev);
snd_soc_unregister_codec(&pdev->dev);
pm_runtime_disable(&pdev->dev); pm_runtime_disable(&pdev->dev);
if (!pm_runtime_status_suspended(&pdev->dev))
tegra210_dmic_runtime_suspend(&pdev->dev);
return 0; return 0;
} }
@@ -619,24 +495,21 @@ static int tegra210_dmic_platform_remove(struct platform_device *pdev)
static const struct dev_pm_ops tegra210_dmic_pm_ops = { static const struct dev_pm_ops tegra210_dmic_pm_ops = {
SET_RUNTIME_PM_OPS(tegra210_dmic_runtime_suspend, SET_RUNTIME_PM_OPS(tegra210_dmic_runtime_suspend,
tegra210_dmic_runtime_resume, NULL) tegra210_dmic_runtime_resume, NULL)
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume) pm_runtime_force_resume)
}; };
static struct platform_driver tegra210_dmic_driver = { static struct platform_driver tegra210_dmic_driver = {
.driver = { .driver = {
.name = DRV_NAME, .name = "tegra210-dmic",
.owner = THIS_MODULE,
.of_match_table = tegra210_dmic_of_match, .of_match_table = tegra210_dmic_of_match,
.pm = &tegra210_dmic_pm_ops, .pm = &tegra210_dmic_pm_ops,
}, },
.probe = tegra210_dmic_platform_probe, .probe = tegra210_dmic_probe,
.remove = tegra210_dmic_platform_remove, .remove = tegra210_dmic_remove,
}; };
module_platform_driver(tegra210_dmic_driver) module_platform_driver(tegra210_dmic_driver)
MODULE_AUTHOR("Rahul Mittal <rmittal@nvidia.com>"); MODULE_AUTHOR("Rahul Mittal <rmittal@nvidia.com>");
MODULE_DESCRIPTION("Tegra210 DMIC ASoC driver"); MODULE_DESCRIPTION("Tegra210 ASoC DMIC driver");
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra210_dmic_of_match);

68
sound/soc/tegra/tegra210_dmic.h
View File

@@ -1,23 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* tegra210_dmic_alt.h - Definitions for Tegra210 DMIC driver * tegra210_dmic.h - Definitions for Tegra210 DMIC driver
* *
* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#ifndef __TEGRA210_DMIC_ALT_H__ #ifndef __TEGRA210_DMIC_H__
#define __TEGRA210_DMIC_ALT_H__ #define __TEGRA210_DMIC_H__
/* Register offsets from DMIC BASE */ /* Register offsets from DMIC BASE */
#define TEGRA210_DMIC_TX_STATUS 0x0c #define TEGRA210_DMIC_TX_STATUS 0x0c
@@ -33,11 +23,6 @@
#define TEGRA210_DMIC_INT_STATUS 0x50 #define TEGRA210_DMIC_INT_STATUS 0x50
#define TEGRA210_DMIC_CTRL 0x64 #define TEGRA210_DMIC_CTRL 0x64
#define TEGRA210_DMIC_DBG_CTRL 0x70 #define TEGRA210_DMIC_DBG_CTRL 0x70
#define TEGRA210_DMIC_DCR_FILTER_GAIN 0x74
#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_0 0x78
#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_1 0x7c
#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_2 0x80
#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_3 0x84
#define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4 0x88 #define TEGRA210_DMIC_DCR_BIQUAD_0_COEF_4 0x88
#define TEGRA210_DMIC_LP_FILTER_GAIN 0x8c #define TEGRA210_DMIC_LP_FILTER_GAIN 0x8c
#define TEGRA210_DMIC_LP_BIQUAD_0_COEF_0 0x90 #define TEGRA210_DMIC_LP_BIQUAD_0_COEF_0 0x90
@@ -50,17 +35,6 @@
#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_2 0xac #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_2 0xac
#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_3 0xb0 #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_3 0xb0
#define TEGRA210_DMIC_LP_BIQUAD_1_COEF_4 0xb4 #define TEGRA210_DMIC_LP_BIQUAD_1_COEF_4 0xb4
#define TEGRA210_DMIC_CORRECTION_FILTER_GAIN 0xb8
#define TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_0 0xbc
#define TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_1 0xc0
#define TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_2 0xc4
#define TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_3 0xc8
#define TEGRA210_DMIC_CORRECTION_BIQUAD_0_COEF_4 0xcc
#define TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_0 0xd0
#define TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_1 0xd4
#define TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_2 0xd8
#define TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_3 0xdc
#define TEGRA210_DMIC_CORRECTION_BIQUAD_1_COEF_4 0xe0
/* Fields in TEGRA210_DMIC_CTRL */ /* Fields in TEGRA210_DMIC_CTRL */
#define CH_SEL_SHIFT 8 #define CH_SEL_SHIFT 8
@@ -69,11 +43,13 @@
#define TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT) #define TEGRA210_DMIC_CTRL_LRSEL_POLARITY_MASK (0x1 << LRSEL_POL_SHIFT)
#define OSR_SHIFT 0 #define OSR_SHIFT 0
#define TEGRA210_DMIC_CTRL_OSR_MASK (0x3 << OSR_SHIFT) #define TEGRA210_DMIC_CTRL_OSR_MASK (0x3 << OSR_SHIFT)
/* Fields in TEGRA210_DMIC_DBG_CTRL */
#define TEGRA210_DMIC_DBG_CTRL_DCR_ENABLE BIT(3) #define DMIC_OSR_FACTOR 64
#define TEGRA210_DMIC_DBG_CTRL_LP_ENABLE BIT(2)
#define TEGRA210_DMIC_DBG_CTRL_SC_ENABLE BIT(1) #define DEFAULT_GAIN_Q23 0x800000
#define TEGRA210_DMIC_DBG_CTRL_BYPASS BIT(0)
/* Max boost gain factor used for mixer control */
#define MAX_BOOST_GAIN 25599
enum tegra_dmic_ch_select { enum tegra_dmic_ch_select {
DMIC_CH_SELECT_LEFT, DMIC_CH_SELECT_LEFT,
@@ -87,19 +63,23 @@ enum tegra_dmic_osr {
DMIC_OSR_256, DMIC_OSR_256,
}; };
enum tegra_dmic_lrsel {
DMIC_LRSEL_LEFT,
DMIC_LRSEL_RIGHT,
};
struct tegra210_dmic { struct tegra210_dmic {
struct clk *clk_dmic; struct clk *clk_dmic;
struct regmap *regmap; struct regmap *regmap;
const char *prod_name; unsigned int audio_ch_override;
int boost_gain; /* with 100x factor */ unsigned int audio_bits_override;
unsigned int ch_select; unsigned int srate_override;
unsigned int mono_to_stereo; unsigned int mono_to_stereo;
unsigned int stereo_to_mono; unsigned int stereo_to_mono;
unsigned int sample_rate_via_control; unsigned int boost_gain;
unsigned int channels_via_control; unsigned int ch_select;
unsigned int osr_val; /* osr value */ unsigned int osr_val;
int lrsel; unsigned int lrsel;
int format_out;
}; };
#endif #endif

992
sound/soc/tegra/tegra210_i2s.c
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File diff suppressed because it is too large Load Diff

272
sound/soc/tegra/tegra210_i2s.h
View File

@@ -1,185 +1,106 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* tegra210_i2s_alt.h - Definitions for Tegra210 I2S driver * tegra210_i2s.h - Definitions for Tegra210 I2S driver
* *
* Copyright (c) 2014-2020 NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#ifndef __TEGRA210_I2S_ALT_H__ #ifndef __TEGRA210_I2S_H__
#define __TEGRA210_I2S_ALT_H__ #define __TEGRA210_I2S_H__
/* Register offsets from TEGRA210_I2S*_BASE */ /* Register offsets from I2S*_BASE */
#define TEGRA210_I2S_RX_ENABLE 0x0
#define TEGRA210_I2S_RX_SOFT_RESET 0x4
#define TEGRA210_I2S_RX_STATUS 0x0c
#define TEGRA210_I2S_RX_INT_STATUS 0x10
#define TEGRA210_I2S_RX_INT_MASK 0x14
#define TEGRA210_I2S_RX_INT_SET 0x18
#define TEGRA210_I2S_RX_INT_CLEAR 0x1c
#define TEGRA210_I2S_RX_CIF_CTRL 0x20
#define TEGRA210_I2S_RX_CTRL 0x24
#define TEGRA210_I2S_RX_SLOT_CTRL 0x28
#define TEGRA210_I2S_RX_CLK_TRIM 0x2c
#define TEGRA210_I2S_RX_CYA 0x30
#define TEGRA210_I2S_RX_CIF_FIFO_STATUS 0x34
#define TEGRA210_I2S_TX_ENABLE 0x40
#define TEGRA210_I2S_TX_SOFT_RESET 0x44
#define TEGRA210_I2S_TX_STATUS 0x4c
#define TEGRA210_I2S_TX_INT_STATUS 0x50
#define TEGRA210_I2S_TX_INT_MASK 0x54
#define TEGRA210_I2S_TX_INT_SET 0x58
#define TEGRA210_I2S_TX_INT_CLEAR 0x5c
#define TEGRA210_I2S_TX_CIF_CTRL 0x60
#define TEGRA210_I2S_TX_CTRL 0x64
#define TEGRA210_I2S_TX_SLOT_CTRL 0x68
#define TEGRA210_I2S_TX_CLK_TRIM 0x6c
#define TEGRA210_I2S_TX_CYA 0x70
#define TEGRA210_I2S_TX_CIF_FIFO_STATUS 0x74
#define TEGRA210_I2S_ENABLE 0x80
#define TEGRA210_I2S_SOFT_RESET 0x84
#define TEGRA210_I2S_CG 0x88
#define TEGRA210_I2S_STATUS 0x8c
#define TEGRA210_I2S_INT_STATUS 0x90
#define TEGRA210_I2S_CTRL 0xa0
#define TEGRA210_I2S_TIMING 0xa4
#define TEGRA210_I2S_SLOT_CTRL 0xa8
#define TEGRA210_I2S_CLK_TRIM 0xac
#define TEGRA210_I2S_CYA 0xb0
#define TEGRA210_I2S_AXBAR_RX_ENABLE 0x0 /* Bit fields, shifts and masks */
#define TEGRA210_I2S_AXBAR_RX_SOFT_RESET 0x4 #define I2S_DATA_SHIFT 8
#define TEGRA210_I2S_AXBAR_RX_STATUS 0x0c #define I2S_CTRL_DATA_OFFSET_MASK (0x7ff << I2S_DATA_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_INT_STATUS 0x10
#define TEGRA210_I2S_AXBAR_RX_INT_MASK 0x14
#define TEGRA210_I2S_AXBAR_RX_INT_SET 0x18
#define TEGRA210_I2S_AXBAR_RX_INT_CLEAR 0x1c
#define TEGRA210_I2S_AXBAR_RX_CIF_CTRL 0x20
#define TEGRA210_I2S_AXBAR_RX_CTRL 0x24
#define TEGRA210_I2S_AXBAR_RX_SLOT_CTRL 0x28
#define TEGRA210_I2S_AXBAR_RX_CLK_TRIM 0x2c
#define TEGRA210_I2S_AXBAR_RX_CYA 0x30
#define TEGRA210_I2S_AXBAR_RX_CIF_FIFO_STATUS 0x34
#define TEGRA210_I2S_AXBAR_TX_ENABLE 0x40
#define TEGRA210_I2S_AXBAR_TX_SOFT_RESET 0x44
#define TEGRA210_I2S_AXBAR_TX_STATUS 0x4c
#define TEGRA210_I2S_AXBAR_TX_INT_STATUS 0x50
#define TEGRA210_I2S_AXBAR_TX_INT_MASK 0x54
#define TEGRA210_I2S_AXBAR_TX_INT_SET 0x58
#define TEGRA210_I2S_AXBAR_TX_INT_CLEAR 0x5c
#define TEGRA210_I2S_AXBAR_TX_CIF_CTRL 0x60
#define TEGRA210_I2S_AXBAR_TX_CTRL 0x64
#define TEGRA210_I2S_AXBAR_TX_SLOT_CTRL 0x68
#define TEGRA210_I2S_AXBAR_TX_CLK_TRIM 0x6c
#define TEGRA210_I2S_AXBAR_TX_CYA 0x70
#define TEGRA210_I2S_AXBAR_TX_CIF_FIFO_STATUS 0x74
#define TEGRA210_I2S_ENABLE 0x80
#define TEGRA210_I2S_SOFT_RESET 0x84
#define TEGRA210_I2S_CG 0x88
#define TEGRA210_I2S_STATUS 0x8c
#define TEGRA210_I2S_INT_STATUS 0x90
#define TEGRA210_I2S_CTRL 0xa0
#define TEGRA210_I2S_TIMING 0xa4
#define TEGRA210_I2S_SLOT_CTRL 0xa8
#define TEGRA210_I2S_CLK_TRIM 0xac
#define TEGRA210_I2S_CYA 0xb0
/* #define I2S_EN_SHIFT 0
* I2S_AXBAAR_RX registers are with respect to AXBAR. #define I2S_EN_MASK BIT(I2S_EN_SHIFT)
* The data is coming from AXBAR to I2S for playback. #define I2S_EN BIT(I2S_EN_SHIFT)
*/
/* Fields in TEGRA210_I2S_AXBAR_RX_ENABLE */ #define I2S_FSYNC_WIDTH_SHIFT 24
#define TEGRA210_I2S_AXBAR_RX_EN_SHIFT 0 #define I2S_CTRL_FSYNC_WIDTH_MASK (0xff << I2S_FSYNC_WIDTH_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_EN (1 << TEGRA210_I2S_AXBAR_RX_EN_SHIFT)
/* Fields in TEGRA210_I2S_AXBAR_RX_CTRL */ #define I2S_POS_EDGE 0
#define TEGRA210_I2S_AXBAR_RX_CTRL_DATA_OFFSET_SHIFT 8 #define I2S_NEG_EDGE 1
#define TEGRA210_I2S_AXBAR_RX_CTRL_DATA_OFFSET_MASK (0x7ff << TEGRA210_I2S_AXBAR_RX_CTRL_DATA_OFFSET_SHIFT) #define I2S_EDGE_SHIFT 20
#define I2S_CTRL_EDGE_CTRL_MASK BIT(I2S_EDGE_SHIFT)
#define I2S_CTRL_EDGE_CTRL_POS_EDGE (I2S_POS_EDGE << I2S_EDGE_SHIFT)
#define I2S_CTRL_EDGE_CTRL_NEG_EDGE (I2S_NEG_EDGE << I2S_EDGE_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_CTRL_MASK_BITS_SHIFT 4 #define I2S_FMT_LRCK 0
#define I2S_FMT_FSYNC 1
#define I2S_FMT_SHIFT 12
#define I2S_CTRL_FRAME_FMT_MASK (7 << I2S_FMT_SHIFT)
#define I2S_CTRL_FRAME_FMT_LRCK_MODE (I2S_FMT_LRCK << I2S_FMT_SHIFT)
#define I2S_CTRL_FRAME_FMT_FSYNC_MODE (I2S_FMT_FSYNC << I2S_FMT_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_SHIFT 1 #define I2S_CTRL_MASTER_EN_SHIFT 10
#define TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_MASK (3 << TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_SHIFT) #define I2S_CTRL_MASTER_EN_MASK BIT(I2S_CTRL_MASTER_EN_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_NOHIGHZ (0 << TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_SHIFT) #define I2S_CTRL_MASTER_EN BIT(I2S_CTRL_MASTER_EN_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_HIGHZ (1 << TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_HIGHZ_ON_HALF_BIT_CLK (2 << TEGRA210_I2S_AXBAR_RX_CTRL_HIGHZ_CTRL_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_SHIFT 0 #define I2S_CTRL_LRCK_POL_SHIFT 9
#define TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_MASK (1 << TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_SHIFT) #define I2S_CTRL_LRCK_POL_MASK BIT(I2S_CTRL_LRCK_POL_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_MSB_FIRST (0 << TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_SHIFT) #define I2S_CTRL_LRCK_POL_LOW (0 << I2S_CTRL_LRCK_POL_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_LSB_FIRST (1 << TEGRA210_I2S_AXBAR_RX_CTRL_BIT_ORDER_SHIFT) #define I2S_CTRL_LRCK_POL_HIGH BIT(I2S_CTRL_LRCK_POL_SHIFT)
/* #define I2S_CTRL_LPBK_SHIFT 8
* I2S_AXBAAR_TX registers are with respect to AXBAR. #define I2S_CTRL_LPBK_MASK BIT(I2S_CTRL_LPBK_SHIFT)
* The data is goint to AXBAR from I2S for capture. #define I2S_CTRL_LPBK_EN BIT(I2S_CTRL_LPBK_SHIFT)
*/
/* Fields in TEGRA210_I2S_AXBAR_TX_ENABLE */ #define I2S_BITS_8 1
#define TEGRA210_I2S_AXBAR_TX_EN_SHIFT 0 #define I2S_BITS_16 3
#define TEGRA210_I2S_AXBAR_TX_EN (1 << TEGRA210_I2S_AXBAR_TX_EN_SHIFT) #define I2S_BITS_32 7
#define I2S_CTRL_BIT_SIZE_MASK 0x7
/* Fields in TEGRA210_I2S_AXBAR_TX_CTRL */ #define I2S_TIMING_CH_BIT_CNT_MASK 0x7ff
#define TEGRA210_I2S_AXBAR_TX_CTRL_DATA_OFFSET_SHIFT 8 #define I2S_TIMING_CH_BIT_CNT_SHIFT 0
#define TEGRA210_I2S_AXBAR_TX_CTRL_DATA_OFFSET_MASK (0x7ff << TEGRA210_I2S_AXBAR_TX_CTRL_DATA_OFFSET_SHIFT)
#define TEGRA210_I2S_AXBAR_TX_CTRL_MASK_BITS_SHIFT 4 #define I2S_SOFT_RESET_SHIFT 0
#define I2S_SOFT_RESET_MASK BIT(I2S_SOFT_RESET_SHIFT)
#define I2S_SOFT_RESET_EN BIT(I2S_SOFT_RESET_SHIFT)
#define TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_SHIFT 1 #define I2S_RX_FIFO_DEPTH 64
#define TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_MASK (3 << TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_SHIFT) #define DEFAULT_I2S_RX_FIFO_THRESHOLD 3
#define TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_NOHIGHZ (0 << TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_SHIFT)
#define TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_HIGHZ (1 << TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_SHIFT)
#define TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_HIGHZ_ON_HALF_BIT_CLK (2 << TEGRA210_I2S_AXBAR_TX_CTRL_HIGHZ_CTRL_SHIFT)
#define TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_SHIFT 0 #define DEFAULT_I2S_SLOT_MASK 0xffff
#define TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_MASK (1 << TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_SHIFT)
#define TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_MSB_FIRST (0 << TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_SHIFT)
#define TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_LSB_FIRST (1 << TEGRA210_I2S_AXBAR_TX_CTRL_BIT_ORDER_SHIFT)
/* Fields in TEGRA210_I2S_ENABLE */
#define TEGRA210_I2S_EN_SHIFT 0
#define TEGRA210_I2S_EN_MASK (1 << TEGRA210_I2S_EN_SHIFT)
#define TEGRA210_I2S_EN (1 << TEGRA210_I2S_EN_SHIFT)
/* Fields in TEGRA210_I2S_CTRL */
#define TEGRA210_I2S_CTRL_FSYNC_WIDTH_SHIFT 24
#define TEGRA210_I2S_CTRL_FSYNC_WIDTH_MASK (0xff << TEGRA210_I2S_CTRL_FSYNC_WIDTH_SHIFT)
#define TEGRA210_I2S_POS_EDGE 0
#define TEGRA210_I2S_NEG_EDGE 1
#define TEGRA210_I2S_CTRL_EDGE_CTRL_SHIFT 20
#define TEGRA210_I2S_CTRL_EDGE_CTRL_MASK (1 << TEGRA210_I2S_CTRL_EDGE_CTRL_SHIFT)
#define TEGRA210_I2S_CTRL_EDGE_CTRL_POS_EDGE (TEGRA210_I2S_POS_EDGE << TEGRA210_I2S_CTRL_EDGE_CTRL_SHIFT)
#define TEGRA210_I2S_CTRL_EDGE_CTRL_NEG_EDGE (TEGRA210_I2S_NEG_EDGE << TEGRA210_I2S_CTRL_EDGE_CTRL_SHIFT)
#define TEGRA210_I2S_CTRL_PIPE_MACRO_EN_SHIFT 19
#define TEGRA210_I2S_CTRL_PIPE_MACRO_EN (1 << TEGRA210_I2S_CTRL_PIPE_MACRO_EN_SHIFT)
#define TEGRA210_I2S_FRAME_FORMAT_LRCK 0
#define TEGRA210_I2S_FRAME_FORMAT_FSYNC 1
#define TEGRA210_I2S_CTRL_FRAME_FORMAT_SHIFT 12
#define TEGRA210_I2S_CTRL_FRAME_FORMAT_MASK (7 << TEGRA210_I2S_CTRL_FRAME_FORMAT_SHIFT)
#define TEGRA210_I2S_CTRL_FRAME_FORMAT_LRCK_MODE (TEGRA210_I2S_FRAME_FORMAT_LRCK << TEGRA210_I2S_CTRL_FRAME_FORMAT_SHIFT)
#define TEGRA210_I2S_CTRL_FRAME_FORMAT_FSYNC_MODE (TEGRA210_I2S_FRAME_FORMAT_FSYNC << TEGRA210_I2S_CTRL_FRAME_FORMAT_SHIFT)
#define TEGRA210_I2S_CTRL_MASTER_EN_SHIFT 10
#define TEGRA210_I2S_CTRL_MASTER_EN_MASK (1 << TEGRA210_I2S_CTRL_MASTER_EN_SHIFT)
#define TEGRA210_I2S_CTRL_MASTER_EN (1 << TEGRA210_I2S_CTRL_MASTER_EN_SHIFT)
#define TEGRA210_I2S_CTRL_SLAVE_EN (1 << TEGRA210_I2S_CTRL_MASTER_EN_SHIFT)
#define TEGRA210_I2S_CTRL_LRCK_POLARITY_SHIFT 9
#define TEGRA210_I2S_CTRL_LRCK_POLARITY_MASK (1 << TEGRA210_I2S_CTRL_LRCK_POLARITY_SHIFT)
#define TEGRA210_I2S_CTRL_LRCK_POLARITY_LOW (0 << TEGRA210_I2S_CTRL_LRCK_POLARITY_SHIFT)
#define TEGRA210_I2S_CTRL_LRCK_POLARITY_HIGH (1 << TEGRA210_I2S_CTRL_LRCK_POLARITY_SHIFT)
#define TEGRA210_I2S_CTRL_LPBK_SHIFT 8
#define TEGRA210_I2S_CTRL_LPBK_MASK (1 << TEGRA210_I2S_CTRL_LPBK_SHIFT)
#define TEGRA210_I2S_CTRL_LPBK_EN (1 << TEGRA210_I2S_CTRL_LPBK_SHIFT)
#define TEGRA210_I2S_BITS_8 1
#define TEGRA210_I2S_BITS_16 3
#define TEGRA210_I2S_BITS_32 7
#define TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT 0
#define TEGRA210_I2S_CTRL_BIT_SIZE_MASK (7 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
#define TEGRA210_I2S_CTRL_BIT_SIZE_8 (TEGRA210_I2S_BITS_8 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
#define TEGRA210_I2S_CTRL_BIT_SIZE_16 (TEGRA210_I2S_BITS_16 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
#define TEGRA210_I2S_CTRL_BIT_SIZE_32 (TEGRA210_I2S_BITS_32 << TEGRA210_I2S_CTRL_BIT_SIZE_SHIFT)
/* Fields in TEGRA210_I2S_TIMING */
#define TEGRA210_I2S_TIMING_CHANNEL_BIT_CNT_MASK 0x3ff
#define TEGRA210_I2S_TIMING_CHANNEL_BIT_CNT_SHIFT 0
/* Fields in TEGRA210_I2S_RX_SOFT_RESET */
#define TEGRA210_I2S_AXBAR_RX_SOFT_RESET_SHIFT 0
#define TEGRA210_I2S_AXBAR_RX_SOFT_RESET_MASK (1 << TEGRA210_I2S_AXBAR_RX_SOFT_RESET_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_SOFT_RESET_EN (1 << TEGRA210_I2S_AXBAR_RX_SOFT_RESET_SHIFT)
#define TEGRA210_I2S_AXBAR_RX_SOFT_RESET_DEFAULT (0 << TEGRA210_I2S_AXBAR_RX_SOFT_RESET_SHIFT)
/* Fields in TEGRA210_I2S_TX_SOFT_RESET */
#define TEGRA210_I2S_AXBAR_TX_SOFT_RESET_SHIFT 0
#define TEGRA210_I2S_AXBAR_TX_SOFT_RESET_MASK (1 << TEGRA210_I2S_AXBAR_TX_SOFT_RESET_SHIFT)
#define TEGRA210_I2S_AXBAR_TX_SOFT_RESET_EN (1 << TEGRA210_I2S_AXBAR_TX_SOFT_RESET_SHIFT)
#define TEGRA210_I2S_AXBAR_TX_SOFT_RESET_DEFAULT (0 << TEGRA210_I2S_AXBAR_TX_SOFT_RESET_SHIFT)
/* Fields in TEGRA210_I2S_SLOT_CTRL */
#define TEGRA210_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT 0
#define TEGRA210_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK 0xf
#define TEGRA210_I2S_RX_FIFO_DEPTH 64
enum tegra210_i2s_path { enum tegra210_i2s_path {
I2S_RX_PATH, I2S_RX_PATH,
@@ -191,24 +112,21 @@ struct tegra210_i2s {
struct clk *clk_i2s; struct clk *clk_i2s;
struct clk *clk_sync_input; struct clk *clk_sync_input;
struct regmap *regmap; struct regmap *regmap;
const char *prod_name; unsigned int stereo_to_mono[I2S_PATHS];
struct regulator_bulk_data *supplies; unsigned int mono_to_stereo[I2S_PATHS];
struct notifier_block slgc_notifier; unsigned int audio_ch_override[I2S_PATHS];
int num_supplies; unsigned int audio_fmt_override[I2S_PATHS];
int bclk_ratio; /* Client overrides are common for TX and RX paths */
int audio_fmt_override[I2S_PATHS]; unsigned int client_ch_override;
int codec_bit_format; unsigned int client_fmt_override;
int sample_rate_via_control; unsigned int srate_override;
int audio_ch_override[I2S_PATHS]; unsigned int dai_fmt;
int client_ch_override; /* common for both TX and RX */
int stereo_to_mono[I2S_PATHS];
int mono_to_stereo[I2S_PATHS];
unsigned int fsync_width; unsigned int fsync_width;
unsigned int bclk_ratio;
unsigned int tx_mask; unsigned int tx_mask;
unsigned int rx_mask; unsigned int rx_mask;
unsigned int rx_fifo_th;
bool loopback; bool loopback;
unsigned int format;
unsigned int rx_fifo_th; /* should be programmed interms of frames */
}; };
#endif #endif