nv-tegra-mirror/linux-nv-oot
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nv-oot.git synced 2025-12-22 09:11:26 +03:00
Code Issues Packages Projects Releases Wiki Activity

nvidia-oot: Fix sparse errors for camera

Browse Source 
Fix below sparse errors:
1. Unused variable.
2. Defined but not used function.
3. Symbol was not declared, should set it to static.
4. No newline at end of file.

Bug 3954363

Change-Id: I3395b66f9acfbf5206713e87063d0e70ad28b4d0
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2878138
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Frank Chen
2023-03-27 21:49:25 -07:00
committed by mobile promotions
parent f6a50b3850
commit be31fa8edb
6 changed files with 13 additions and 99 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/media/platform/tegra/camera/nvcsi/csi5_fops.c
View File

@@ -2,7 +2,7 @@
/*
* Tegra CSI5 device common APIs
*
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/log2.h>
#include <media/csi.h>
@@ -516,4 +516,4 @@ struct tegra_csi_fops csi5_fops = {
.hw_init = csi5_hw_init,
.tpg_set_gain = csi5_tpg_set_gain,
};
EXPORT_SYMBOL(csi5_fops);
EXPORT_SYMBOL(csi5_fops);

4
drivers/platform/tegra/rtcpu/camchar.c
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include <linux/bitmap.h>
#include <linux/cdev.h>
@@ -398,7 +398,7 @@ static struct tegra_ivc_driver camchar_driver = {
.ops.channel = &tegra_ivc_channel_chardev_ops,
};
tegra_ivc_subsys_driver(camchar_driver, tegra_camchar_init, tegra_camchar_exit);
module_driver(camchar_driver, tegra_camchar_init, tegra_camchar_exit);
MODULE_AUTHOR("Jan Solanti <jsolanti@nvidia.com>");
MODULE_DESCRIPTION("The character device for ivc-bus");
MODULE_LICENSE("GPL v2");

3
drivers/platform/tegra/rtcpu/ivc-bus.c
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include <linux/kernel.h>
#include <linux/module.h>
@@ -78,7 +78,6 @@ static struct tegra_ivc_channel *tegra_ivc_channel_create(
struct tegra_ivc_region *region,
struct camrtc_hsp *camhsp)
{
struct device *peer_device = bus->dev.parent;
struct camrtc_tlv_ivc_setup *tlv;
struct {
u32 rx;

85
drivers/platform/tegra/tegra-camera-rtcpu-base.c
View File

@@ -71,18 +71,6 @@ static int tegra_rce_cam_wait_for_idle(struct device *dev);
static void tegra_rce_cam_assert_resets(struct device *dev);
static int tegra_rce_cam_deassert_resets(struct device *dev);
static const char * const sce_reset_names[] = {
"nvidia,reset-group-1",
"nvidia,reset-group-2",
NULL,
};
static const char * const sce_reg_names[] = {
"sce-pm",
"sce-cfg",
NULL
};
static const char * const rce_reset_names[] = {
"reset-names", /* all named resets */
NULL,
@@ -353,79 +341,6 @@ static void tegra_camrtc_set_fwloaddone(struct device *dev, bool fwloaddone)
}
}
static int tegra_sce_cam_deassert_resets(struct device *dev)
{
struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev);
int err;
err = camrtc_reset_group_deassert(rtcpu->resets[0]);
if (err)
return err;
/* Configure R5 core */
if (rtcpu->cfg_base != NULL) {
u32 val = readl(rtcpu->cfg_base + TEGRA_APS_FRSC_SC_CTL_0);
if (val != TEGRA_R5R_SC_DISABLE) {
/* Disable R5R and smartcomp in camera mode */
writel(TEGRA_R5R_SC_DISABLE,
rtcpu->cfg_base + TEGRA_APS_FRSC_SC_CTL_0);
/* Enable JTAG/Coresight */
writel(TEGRA_FN_MODEIN,
rtcpu->cfg_base + TEGRA_APS_FRSC_SC_MODEIN_0);
}
}
/* Group 2 */
err = camrtc_reset_group_deassert(rtcpu->resets[1]);
if (err)
return err;
/* Group 3: nCPUHALT controlled by PM, not by CAR. */
tegra_camrtc_set_fwloaddone(dev, true);
return 0;
}
static void tegra_sce_cam_assert_resets(struct device *dev)
{
struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev);
tegra_camrtc_set_fwloaddone(dev, false);
camrtc_reset_group_assert(rtcpu->resets[1]);
camrtc_reset_group_assert(rtcpu->resets[0]);
}
static int tegra_sce_cam_wait_for_idle(struct device *dev)
{
struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev);
long timeout = rtcpu->cmd_timeout;
long delay_stride = HZ / 50;
if (rtcpu->pm_base == NULL)
return 0;
/* Poll for WFI assert.*/
for (;;) {
u32 val = readl(rtcpu->pm_base + TEGRA_PM_PWR_STATUS_0);
if ((val & TEGRA_PM_WFIPIPESTOPPED) == 0)
break;
if (timeout < 0) {
dev_warn(dev, "timeout waiting for WFI\n");
return -EBUSY;
}
msleep(delay_stride);
timeout -= delay_stride;
}
return 0;
}
static int tegra_rce_cam_wait_for_idle(struct device *dev)
{
struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev);

8
drivers/video/tegra/camera/tegra_camera_platform.c
View File

@@ -225,13 +225,16 @@ static int tegra_camera_isomgr_unregister(struct tegra_camera_info *info)
static int tegra_camera_isomgr_request(
struct tegra_camera_info *info, uint iso_bw, uint lt)
{
#if defined(CONFIG_TEGRA_ISOMGR)
int ret = 0;
#endif
dev_dbg(info->dev,
"%s++ bw=%u, lt=%u\n", __func__, iso_bw, lt);
#if IS_ENABLED(CONFIG_INTERCONNECT) && IS_ENABLED(CONFIG_TEGRA_T23X_GRHOST)
if (tegra_get_chip_id() == TEGRA234) {
int ret = 0;
/* VI6 does not tolerate DVFS, so we need to request max DRAM floor */
ret = icc_set_bw(info->icc_iso_path_handle,
iso_bw, UINT_MAX);
@@ -426,7 +429,7 @@ int tegra_camera_update_isobw(void)
struct tegra_camera_info *info;
unsigned long total_khz;
unsigned long bw;
#ifdef CONFIG_TEGRA_MC
#ifdef CONFIG_NV_TEGRA_MC
unsigned long bw_mbps;
#endif
int ret = 0;
@@ -576,8 +579,6 @@ static long tegra_camera_ioctl(struct file *file,
case _IOC_NR(TEGRA_CAMERA_IOCTL_GET_BW):
{
unsigned long mc_hz = 0;
u64 bw = 0;
#if IS_ENABLED(CONFIG_INTERCONNECT) && IS_ENABLED(CONFIG_TEGRA_T23X_GRHOST)
if (tegra_get_chip_id() == TEGRA234) {
dev_err(info->dev,
@@ -587,7 +588,6 @@ static long tegra_camera_ioctl(struct file *file,
}
#endif
return -EFAULT;
break;
}

8
drivers/video/tegra/host/vi/vi5.c
View File

@@ -2,7 +2,7 @@
/*
* VI5 driver
*
* Copyright (c) 2017-2022, NVIDIA Corporation. All rights reserved.
* Copyright (c) 2017-2023, NVIDIA Corporation. All rights reserved.
*/
#include <asm/ioctls.h>
@@ -284,7 +284,7 @@ static int vi5_remove(struct platform_device *pdev)
return 0;
}
struct nvhost_device_data t19_vi5_info = {
static struct nvhost_device_data t19_vi5_info = {
.devfs_name = "vi",
.moduleid = 2, //NVHOST_MODULE_VI,
.clocks = {
@@ -300,7 +300,7 @@ struct nvhost_device_data t19_vi5_info = {
.bwmgr_client_id = TEGRA_BWMGR_CLIENT_VI,
};
struct nvhost_device_data t23x_vi0_info = {
static struct nvhost_device_data t23x_vi0_info = {
.devfs_name = "vi0",
.moduleid = 2, //NVHOST_MODULE_VI,
.clocks = {
@@ -312,7 +312,7 @@ struct nvhost_device_data t23x_vi0_info = {
.post_virt_init = vi5_priv_late_probe,
};
struct nvhost_device_data t23x_vi1_info = {
static struct nvhost_device_data t23x_vi1_info = {
.devfs_name = "vi1",
.moduleid = 3, //NVHOST_MODULE_VI2,
.clocks = {