nvidia-oot: Fix sparse errors for camera

Fix below sparse errors:
1. Unused variable.
2. Defined but not used function.
3. Symbol was not declared, should set it to static.
4. No newline at end of file.

Bug 3954363

Change-Id: I3395b66f9acfbf5206713e87063d0e70ad28b4d0
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2878138
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Frank Chen
2023-03-27 21:49:25 -07:00
committed by mobile promotions
parent f6a50b3850
commit be31fa8edb
6 changed files with 13 additions and 99 deletions

View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include <linux/bitmap.h>
#include <linux/cdev.h>
@@ -398,7 +398,7 @@ static struct tegra_ivc_driver camchar_driver = {
.ops.channel = &tegra_ivc_channel_chardev_ops,
};
tegra_ivc_subsys_driver(camchar_driver, tegra_camchar_init, tegra_camchar_exit);
module_driver(camchar_driver, tegra_camchar_init, tegra_camchar_exit);
MODULE_AUTHOR("Jan Solanti <jsolanti@nvidia.com>");
MODULE_DESCRIPTION("The character device for ivc-bus");
MODULE_LICENSE("GPL v2");

View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include <linux/kernel.h>
#include <linux/module.h>
@@ -78,7 +78,6 @@ static struct tegra_ivc_channel *tegra_ivc_channel_create(
struct tegra_ivc_region *region,
struct camrtc_hsp *camhsp)
{
struct device *peer_device = bus->dev.parent;
struct camrtc_tlv_ivc_setup *tlv;
struct {
u32 rx;

View File

@@ -71,18 +71,6 @@ static int tegra_rce_cam_wait_for_idle(struct device *dev);
static void tegra_rce_cam_assert_resets(struct device *dev);
static int tegra_rce_cam_deassert_resets(struct device *dev);
static const char * const sce_reset_names[] = {
"nvidia,reset-group-1",
"nvidia,reset-group-2",
NULL,
};
static const char * const sce_reg_names[] = {
"sce-pm",
"sce-cfg",
NULL
};
static const char * const rce_reset_names[] = {
"reset-names", /* all named resets */
NULL,
@@ -353,79 +341,6 @@ static void tegra_camrtc_set_fwloaddone(struct device *dev, bool fwloaddone)
}
}
static int tegra_sce_cam_deassert_resets(struct device *dev)
{
struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev);
int err;
err = camrtc_reset_group_deassert(rtcpu->resets[0]);
if (err)
return err;
/* Configure R5 core */
if (rtcpu->cfg_base != NULL) {
u32 val = readl(rtcpu->cfg_base + TEGRA_APS_FRSC_SC_CTL_0);
if (val != TEGRA_R5R_SC_DISABLE) {
/* Disable R5R and smartcomp in camera mode */
writel(TEGRA_R5R_SC_DISABLE,
rtcpu->cfg_base + TEGRA_APS_FRSC_SC_CTL_0);
/* Enable JTAG/Coresight */
writel(TEGRA_FN_MODEIN,
rtcpu->cfg_base + TEGRA_APS_FRSC_SC_MODEIN_0);
}
}
/* Group 2 */
err = camrtc_reset_group_deassert(rtcpu->resets[1]);
if (err)
return err;
/* Group 3: nCPUHALT controlled by PM, not by CAR. */
tegra_camrtc_set_fwloaddone(dev, true);
return 0;
}
static void tegra_sce_cam_assert_resets(struct device *dev)
{
struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev);
tegra_camrtc_set_fwloaddone(dev, false);
camrtc_reset_group_assert(rtcpu->resets[1]);
camrtc_reset_group_assert(rtcpu->resets[0]);
}
static int tegra_sce_cam_wait_for_idle(struct device *dev)
{
struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev);
long timeout = rtcpu->cmd_timeout;
long delay_stride = HZ / 50;
if (rtcpu->pm_base == NULL)
return 0;
/* Poll for WFI assert.*/
for (;;) {
u32 val = readl(rtcpu->pm_base + TEGRA_PM_PWR_STATUS_0);
if ((val & TEGRA_PM_WFIPIPESTOPPED) == 0)
break;
if (timeout < 0) {
dev_warn(dev, "timeout waiting for WFI\n");
return -EBUSY;
}
msleep(delay_stride);
timeout -= delay_stride;
}
return 0;
}
static int tegra_rce_cam_wait_for_idle(struct device *dev)
{
struct tegra_cam_rtcpu *rtcpu = dev_get_drvdata(dev);