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spi: tegra210-quad: fix combined sequence programming

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Fix the failures observed in combined sequence programming
while validating qspi flash on orin platforms.

Change-Id: Ifd404eebfc1480f328c58930c95b30903f2d3269
Signed-off-by: Vishwaroop A <va@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2869997
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Vishwaroop A
2023-03-13 10:32:33 +00:00
committed by mobile promotions
parent dab2a32da0
commit dd88969020
1 changed files with 3 additions and 1 deletions
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4
drivers/spi/spi-tegra210-quad.c
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@@ -1117,11 +1117,13 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
address_value = *((const u32 *)(xfer->tx_buf));
break;
case DUMMY_TRANSFER:
case DATA_TRANSFER:
if (xfer->dummy_data) {
tqspi->dummy_cycles = xfer->len * 8 / xfer->tx_nbits;
break;
} else {
transfer_phase++;
}
case DATA_TRANSFER:
/* Program Command, Address value in register */
tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD);
tegra_qspi_writel(tqspi, address_value,