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nvadsp: Clear HWBOX0 for ADSP guest reset handling

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During ADSP playback, if HWMBOX0 is high and guest reset is
done, after reset ADSP is unable to communicate with kernel
driver since the interrupt line remains High thereby not
generating interrupt (edge triggered).

Jira EMA-1178

Change-Id: Ifb1283c7286ed944f243e7d92dfe4db40bcd0ba2
Signed-off-by: Hariharan Sivaraman <hariharans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1978017
Reviewed-by: Uday Gupta <udayg@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dipesh Gandhi <dipeshg@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Hariharan Sivaraman
2018-12-21 16:22:56 +05:30
committed by Laxman Dewangan
parent 989d49990e
commit ee8de73c70
1 changed files with 3 additions and 0 deletions
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3
drivers/platform/tegra/nvadsp/os-t18x.c
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@@ -87,6 +87,9 @@ int nvadsp_os_t18x_init(struct platform_device *pdev)
/* Write to HWMBOX5 */
hwmbox_writel(val, drv_data->chip_data->hwmb.hwmbox5_reg);
/* Clear HWMBOX0 for ADSP Guest reset handling */
hwmbox_writel(0, drv_data->chip_data->hwmb.hwmbox0_reg);
return 0;
}