Earlier hardcoded pll base rates were leading to fractional divider
values for i2s multichannel config while deriving i2s bclk.
Hence updated clock rates and logic for >2 channel configs for t186ref
and higher boards such that the dynamic range between max plla and min plla
is < 35 MHz. Also, if desired bclk is above limit, the case will be
declared as not supported. Note that new facility will be used only in l4t
machine driver.
Bug 200702569
Change-Id: I83aba425f6dde30a1f29f85b16a1bbbebba14198
Signed-off-by: Asha Talambedu <atalambedu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2491744
(cherry picked from commit e0fe51d5e7ced073eb618e19836f88a023f70bdc)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.10/+/2613507
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Mohan Kumar D <mkumard@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tegra Audio HW subsystem has many I/O module instances and currently a
single PLL source is used for all these modules. Any I2S configuration
is supported now by dynamically updating PLL base rate. But as of today
this has few limitations.
- AUD_MCLK factor is not considered while updating PLL base rate.
- Two module instances can request conflicting PLL base rate and
the last request overrides existing session. This would also mean
simultaneous 8x and 11x configurations are not possible.
- Tegra210 has problems with specific PLL requests.
Multiple PLLs would be required if concurrent audio sessions need to be
supported and dynamic rate update is needed to support any configuration.
But this has few limitions too.
- Since number of available PLLs for modules are limited, specific PLL
cannot be dedicated to a module. The PLL would be shared and may
cause problems when there are simultaneous conflicting requirements.
- Logic for runtime distribution of PLLs to modules and rate updates
has to be managed in module drivers only as machine driver does not
have intelligence to know for which audio path exactly the hw_param()
call comes. This can make the code complicated and buggy where each
module driver tries to control specific PLL.
Instead the problem can be simplified by fixing PLL rates in DT. User
can employ one or more PLLs to realize their design. Of course this won't
support all configurations simultaneously since this is not what users
require generally. They have specific requirements which can be addressed
via DT configurations. For example,
- Some users may use single PLL and decide on compatible set of audio
configurations for their use cases.
- Some users may want to use two PLLs, one each for 8x and 11x. Then
via DT specific modules can use specific PLL sources to realize
simultaneous 8x and 11x configurations. In fact two PLLs can be
used when there are conflicting requirements which cannot be met
by a single PLL source.
To realize above add new DT property "fixed-pll" and bypass PLL rate
updates from the driver. Users can populate this in their platform
sound DT node, whenever static configurations are preferred.
Bug 200726704
Change-Id: I0416f201fd26c49bb6c09594d86394c46a0bbad2
(cherry-picked from commit 0c84a3fe1e2e40d20ddb449a948da6fdebd85efe)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2548361
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Change-Id: I51d5b502f728baee2d6d075951dc186503cbf76f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.10/+/2556536
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Resolve linux-5.8-rc3 merge conflicts in k5.9 branch
(currently tracking mainline with linux-5.7.0)
Fix build errors in k5.9 branch after merge of linux-5.8-rc3
bug 200617764
Change-Id: I3a358fef6e8b7c5926fd0de05a03cee539547e8f
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
This patch enables Tegra machine driver used on Jetson platform.
Tegra210 and later Jetson platforms use the same machine driver.
Following is the summary from the patch:
* Enable the driver build in defconfig
* Remove "tegra-alt" ASoC utility file
* Renmae "tegra-alt" parser source file "tegra_asoc_dt_parser.c"
to "tegra_asoc_machine.c" and move it to "tegra" directory.
* Similarly "tegra_asoc_machine_alt.h" is renamed to
"tegra_asoc_machine.h" and moved to "tegra".
* Updated "tegra" ASoC utility files for supporting Tegra210 and
later.
* Rename machine driver file.
* The older parsing code is removed.
Bug 2845498
Change-Id: I42d9d2da59febb99ce00a29ce65d7a16f96b1327
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details you should have received a copy of the gnu general
public license along with this program if not write to the free
software foundation inc 51 franklin st fifth floor boston ma 02110
1301 usa
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 246 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190530000436.674189849@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Tegra124 introduces some small changes to the layout of some registers.
Modify the affected drivers to program those registers appropriately
based on which SoC they're running on.
Tegra124 also introduced some new modules on the AHUB configlink register
bus. These will require new entries in configlink_clocks[] in the AHUB
driver. However, supporting that change likely relies on switching Tegra
to the common reset framework, so I'll defer that change for now.
Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Based-on-work-by: Songhee Baek <sbaek@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Tegra114 requires different PLL rates. Modify the code to know about
this.
On Tegra114 only for now, use regular clk_get() rather than clk_get_sys()
to retrieve clocks. This assumes that the clocks will be represented in
device tree. We can assure that from the start of any Tegra114 audio
support. For older chips, I'll add the required clocks properties to the
device trees this kernel cycle, and switch this code to only support the
"new_clocks" path next cycle.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tegra30 has some additional clocks that need to be manipulated, names
some clocks differently, runs PLLs at different base rates, etc. The
utility code needs to handle this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Only the clock programming code needs to know whether the clocks changed,
and that is encapsulated within tegra_asoc_utils_set_rate(). The machine
driver's call to snd_soc_dai_set_sysclk(codec_dai, ...) is safe
irrespective of whether the clocks changed.
(Applying Mark's TrimSlice review comments to the existing driver)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Instead, have the machine driver provide storage for the utility data
somehow.
For Harmony in particular, store this within struct tegra_harmony, itself
referenced by snd_soc_card's drvdata.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Many portions of Tegra ASoC machine drivers will be similar or identical.
To avoid cut/paste, this file will act as a repository for all that common
code. For now, it solely includes code to reprogram the audio PLL for
44.1KHz- vs. 48KHz-based sample rates.
Signed-Off-By: Stephen Warren <swarren@nvidia.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
