pci_client abstraction supports notification to application.
Each endpoint has to register with pci_client for notification which
return link_event_id after registration.
link_event_id is index in lookup table with total size as MAX_ENDPOINT.
This link_event_id is allocated sequential and does not match with ep_id
which is endpoint index with max as MAX_ENDPOINT.
stream-extension is not aware about link_event_id and uses ep_id for
notification which leads to mismatch in look up table finally dropping
notification.
Registering for link event in sequential manner does not help much as
registration against ep_id will make lookup table and endpoint database
one-to-one mapping.
Update endpoint registration for link event based on ep_id and use ep_id
in lookup table for notification purpose.
Bug 4913236
Change-Id: I75bfdbf0e8e5b7b11b0cca7dc266f01f492362f6
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3233789
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Tested-by: Janardhan Reddy AnnapuReddy <jreddya@nvidia.com>
Not all kernel define the enum UFSHCD_QUIRK_BROKEN_PWR_SEQUENCE
Add conftest to find out whether kernel has define the enum
UFSHCD_QUIRK_BROKEN_PWR_SEQUENCE or not and then check for macro
before using it.
Bug 4911768
Change-Id: I4eba6f02ab79c1d4a5bdefb3ec831cc4ae34d527
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
GO bit will be cleared after driver
writing it to 1. Need to check the
clear status. Added check for the same.
Bug 4782274
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I71f035a27fb95de3e37d515a34c48c493f827a44
Set utmi_pll1 as parent for cpu_isc clocks
Bug 4782274
Change-Id: Iab71527dc6de3f46d4b7880c3dd00eadc130c5ba
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
dev_err is used for information prints.
Changed them to dev_info and dev_dbg.
Bug 4736849
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I990edef75566ca718fab611b36385f6ec5f12c44
Read fuse to check if chip has RDL fix or not.
Return error for non-RDL chips.
Bug 4243018
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: Ibe441ca136c18e03cebbc1cd5d0cc529d45005c6
UFS parent clock in T264 is pllrefufs_clkout624
and the rate is to 208 MHz.
Bug 4199271
Change-Id: I5b86e199f93fc1c81506cb29391b96efdc7de3a4
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Set HCLKDIV to 0xD0 as per IAS.
Bug 4199271
Change-Id: I4779c74c657d8723a27a167096dfac9d22128436
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Use conftest for finding whether APIs tegra264_io_pad_power_*
are available or not before using it.
Bug 4911768
Change-Id: Ic8df4a0109a270d5a486a67900ed7fe4c57b79be
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
The change to write the INTF_CRC_CFG register was inadvertently
left out. Correct this.
Bug 4809300
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Change-Id: I208da56d03e90e72ce26dffe7bef1cdeab95fab6
Update the misc register programming for T264
for slave.
Bug 4711327
Change-Id: Ia6409bbee66e9984f83ad792d67c730fa637f58d
Signed-off-by: Vishwaroop A <va@nvidia.com>
Add support to profile NvHost IPs on various chips
by HWPM module.
Bug 4170421
DOS-SHR-7966
Signed-off-by: vasukis <vasukis@nvidia.com>
Change-Id: I42ac3b5fa79d7b6f97e66098cb84277cda2aff4d
T264 has 1MHz clock for tach. Add support for this
clock.
Signed-off-by: Vishwaroop A <va@nvidia.com>
Change-Id: Ic2ecc5dd2494f3b55340f1b925ca616c4844ed6f
Tegra264 use a different base address than Tegra234.
Update the logic of parsing Base Timer and WDT index from iomem resource
beginning.
Bug 4729969
Change-Id: I68d4f03373d2d648c1cf3b82bf74972361693bb5
Signed-off-by: Kartik <kkartik@nvidia.com>
Add support for T264 which has four I2C/DP-AUX instances and four
separate registers to configure each of it. The four registers are
in consecutive addresses, but follow the same bitmap as T234.
T264 I2C <-> DPAUX map is as below:
I2C6 <-> DPAUX0
I2C10 <-> DPAUX1
I2C4 <-> DPAUX2
I2C8 <-> DPAUX3
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Change-Id: I0a38a9a96894fc2d9bb1c0647f4f9cf06e13aaf1
Adding support in existing mttcan driver to control T264 FSI
CAN controllers from CCPLEX whether FSI firmware is loaded on
system or not. FSI CAN clocks will be enabled by FSI crystal clock
upon boot. SW does not need to enable or control clocks. CCPLEX cannot
control FSI controller resets, reset can be handled during boot, thus
disabled clocks and reset for T264 SOC.
Bug 4317516
Change-Id: I8e6b20640c8763ebc0a9d9192e3212a49902f9b4
Signed-off-by: Shubhi Garg <shgarg@nvidia.com>
For Tegra264, new PMC driver is introduced to support instance specific
driver data. As per the design, on Tegra264, if client drivers are using
below PMC exported APIs, they need to pass their struct device pointer
as an argument. Also it is expected that clients dt node should have
"nvidia,pmc" property populated with appropriate PMC instance phandle.
- *_io_pad_power_enable()
- *_io_pad_power_disable()
Bug 4470933
Change-Id: Idb41b95cd863f313496110a4e3c4b5ea61a1df8f
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
- Add compatible and chip data for T264 ADSP[1:0] and AON
- Add T264 dev files to build makefile
DNS
Bug 3682950
Bug 4165898
Change-Id: Idbaef1950ff2f736c7844ee0525d55b596b11132
Signed-off-by: Viswanath L <viswanathl@nvidia.com>
Same compatible string can be shared between host1x_next and
host1x_fence kernel modules so that those two modules will get
automatically loaded.
Bug 4291144
Signed-off-by: Johnny Liu <johnliu@nvidia.com>
Change-Id: I9901f4e094d1d6484f6d6cec6b9890c9a51ad1f6
host1x-fence driver is updated to support t264.
Bug 4132685
Change-Id: I239d12864d6336cc6acca2265dbec3cd05ee629b
Signed-off-by: jianjunm <jianjunm@nvidia.com>
