As per info received from HW team, we should not hardcode 1600 in DRAM
clock to MC clock conversion function. DRAM clk to EMC clk ratio is
always 4:1 while EMC clk to MC clk ratio can be found in CAR register
CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0.MC_EMC_SAME_FREQ bit.
If it's 0 then MC frequency is half of EMC frequency, otherwise MC freq
is same as EMC freq. Hence update DRAM clock to MC clock function as per
above logic.
Bug 4090660
Change-Id: I5a7586aeee29fe1c98437cf0dd5b820d8f540072
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/2915138
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
mc-utils driver should support the following functionality on T264.
Update mc-utils driver for these functionalities for T264:
- EMC freq to BW conversion
- BW to freq conversion
- DRAM clock to MC clock coversion
Bug 4090660
Change-Id: If5ee54d49024d03620dad01049fe35bbcaf3f812
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/2900181
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
mc-utils driver support is needed on T264, and it should be present in
nvidia-t264 repo, so as to avoid leaking any information. Also, we need
to make sure once T264 is public the existing mc-utils driver can be
updated easily for T264 support.
Hence first copy the existing mc-utils driver from nvidia-oot into
nvidia-t264, then make changes for T264 and finally when T264 is public,
just cherry-pick the addional changes in nvidia-oot and clean up driver
from nvidia-t264. This change is doing the first step i.e. copying
existing mc-utils driver code from nvidia-oot into nvidia-t264.
Bug 4090660
Change-Id: I95eff8d3f7fef267a5c0f0e2137c4343a615d4aa
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/2911970
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Remove some of the files which were added as optional for
non-existing of T264 patches. As T264 OOT drivers are
collapsing into the core tree, remove such optional files.
Change-Id: I83116585369f4893d14b527356752fbf2a9a80c8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
- Revamp the core logic to use the portability layer.
- Introduce ping debugfs node.
Bug:
- Update the abort retry logic for -EAGAIN error code. In
the absence of this logic, the queue becomes unavailable
due to race between the reset and the flush command.
Jira DLA-7294
Jira DLA-7310
Change-Id: I9f54f14334736189a00d2236f374188c2bac6155
Signed-off-by: Arvind M <am@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3196673
Reviewed-by: Akshata Bhat <akshatab@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
[1] In the event of busy CPU, the delayed interrupt or the
delayed callback from nvhost will result in the submission
failure.
[2] This commit fixes the issue by performing mandatory and controlled
cleanups.
- Atmost 2 slots are cleaned up prior to the submission.
- Complete queue cleanup during the suspend preparation.
- Complete queue cleanup after successful abort operation.
[3] Additionally, the commit fixes some potential leaks in the error
path.
Bug 4503438
Bug 4414867
Change-Id: Ic40f0c4b1f3c653d5d5e613adab01d3cbc3b9722
Signed-off-by: Arvind M <am@nvidia.com>
Signed-off-by: Akshata Bhat <akshatab@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3105861
(cherry picked from commit 438e8f8e96483971798e2d9014ed4a999143d082)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3120798
(cherry picked from commit 5668f6439643d44b3384bcd750a645d8db6ee0c9)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3196672
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
Skip T264 PCIE drivers for the few kernels like jammy-src, rhivos-1 and
stable.
Bug 4911768
Change-Id: I198fb279712594a69950b72d6b8f14a9ef151e5f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
To avoid the duplicate function defintion between the header and
source, use the proper config to protect it.
Bug 4911768
Change-Id: I8d6880833c122eb2eb7194929eb5ea2cb78a9c45
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Add support for handling the PEX WAKE GPIO (pex_wake_gpiod) by
parsing the pex-wake GPIO from the device tree and setup the
interrupt line.
Enable and disable the wake-up interrupt during system
suspend/resume.
Bug 4788812
Change-Id: Ie8936aa9cc551db1a5d24b277b091de5fbc0439e
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3212875
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
When Root port applies secondary bus reset(SBR) or link disable, EP_RESET
interrupt is received at Endpoint. On EP_RESET poll for detect reset LTSSM
state which confirms that SBR reset released or link disable is cleared.
After polling perform Endpoint controller cold reset.
Due to HW bug 4777981, C2 x2/x1 LTSSM state doesn't move to detect reset
when SBR reset is released, instead it stays in hot reset state. In this
case perform Endpoint controller cold reset after poll timeout. PCIe link
still comes up in this case.
Bug 4777981
Bug 4785875
Change-Id: I89402aa7c963082510170b88a1f7a4ec481162be
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3197116
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Issue:
When XDMA interrupt is received and only error is set, interrupt is not
processed resulting in DMA HW halt and no further transfers working.
Fix:
Process XDMA irq, when either transfer complete or error status is set.
Bug 4747322
Change-Id: Ic71f3bf93343e986a1f4be9b570bcc36f03afeeb
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3175952
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tegra DMA driver functions are defined in nvidia-t264 repo and these
functions are used in nvidia-oot repo. Prototypes of these functions
are defined in nvidia-oot repo header file tegra-pcie-dma.h. Enable
CONFIG_PCIE_TEGRA_DMA flag to expose the function prototypes to the
drivers in nvidia-oot repo. This functions should be exposed only if
nvidia-t264 drivers are included in kernel compilation.
Bug 4712065
Change-Id: I74bb98bd9efbf2e36ed05aae866760a92a4ee7dd
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3164961
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
When PCIe link is disabled or secondary bus reset is done by RP,
EP LTSSM state goes to link disable or hot reset respectively.
Update the LTSSM state check accordingly to support link disable
and secondary bus reset.
XTL_EP_PRI_BAR_CONFIG and XTL_EP_PRI_RESIZE_BAR1 are part of
hot reset domain, when link is going through hot reset, these
registers are not accessible. So, remove these register programming
in tegra264_pcie_ep_clear_bar(). After hot reset these registers
come back with reset values.
Bug 4712053
Change-Id: Ieaf37ed9fed6722db8a16027947121b1cfd1ef4c
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3163927
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
When XDMA error is observed driver resets the XDMA engine.
xdma_ll_ch_init() function is called to reinitialize the
XDMA engine. Incorrect value is passed as the argument for
channel type. Fix this issue by using correct variable for
channel type.
Bug 4707453
Change-Id: Ic06563d599bfd7c0979c9db0a20cebeaa18fe3c8
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3163925
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
The pci_epc_features structure was updated in Linux v6.9 to move various
fields under a new pci_epc_bar_desc structure. Use conftest to determine
if the new pci_epc_bar_desc structure is present.
Finally, add the endpoint alignment for the inbound ATU on Tegra264
which is 64kB.
Bug 4627271
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Change-Id: I074e19ca53cea0e13d9872b240a023dd83779ae7
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3129630
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
The only functions needed from the private pci.h header are
pci_dev_is_disconnected() and of_get_pci_domain_nr().
Starting with Linux v6.9, pci_dev_is_disconnected() has been moved to
the public header and now the private header conflicts with the public
due to multiple definitions. It is better to remove the private pci.h
header file and backport the upstream change that moves the definition
of pci_dev_is_disconnected() to the public header.
With regard to the function of_get_pci_domain_nr(), just declare an
extern for the function prototype in the driver file rather than
copying the entire kernel header.
Bug 4471899
Change-Id: I10e7c3c6a92e9ba87153b2682cc3e69ced8c1a31
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3117272
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Per PCIe r5.0, 6.6.1 wait for 100 ms after DLL up. Optimize PCIe link up
poll logic. Add resume_noirq() callback back function in PCIe driver and
call tegra264_pcie_init() to deassert PERST# and get PCIe link up.
Also, fix minor coding style issues.
Bug 4404453
Change-Id: Iad2d22166eb0c80a20b74ada2ee2766f8d3e174f
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3107413
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Remvoe the existing makefile as preparation to merge T264 specific
PCIE drivers into core repo.
Bug 4911768
Change-Id: Ifa65e36b5253bf2dc4ab62fe8caaf10a53e7cff3
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
- Move chip data from patch files to dev-*.c files for
ease of maintenance
- Add patch file to patch compatible and chip data into
dev.c file, also add dev-*.c files to build makefile
- Add stub for dump_core_state function pointer
- ADSP updates
- Use AMISC base directly from reg DT prop as it will
be offset as per the DSP instance (drop adsp_prid)
- Set amc_not_avlbl to true for ADSP[1], so only ADSP[0]
will access AMC
- Change compatible of ADSP[0] to "nvidia,tegra264-adsp"
in order to keep continuity with previous chip
generations (unique identifier string is "adsp")
Also remove T264 adsp support from kprev.
Bug 3682950
Bug 4165898
Change-Id: I22abf3fda01f4e0e259759ba1816a9580a474d40
Signed-off-by: Viswanath L <viswanathl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3107870
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Asha T <atalambedu@nvidia.com>
Do not build PVA for android kernel as this is not
required for Android.
Bug 4911768
Change-Id: Ibc35c074a8a340afa57cd634e00399e408a416fb
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
In RRA mode, HWSEQ buffer should be validated for each frame.
However, at present, the validation is being done only for
the first frame. Fix this.
Also, record which descriptors will be used in RRA mode as this
information is needed elsewhere in the driver.
Bug 4245426
Change-Id: Ibe572f43350faba27f2e973d6e39ac6e6a4ad1c9
Signed-off-by: abhinayaa <abhinayaa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/2988532
Reviewed-by: Amruta Sai Anusha Bhamidipati <abhamidipati@nvidia.com>
Reviewed-by: Omar Nemri <onemri@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- T26x support 304 ADBs compared to 272 on T23x. Add code to support
this distinction.
- T26x introduces the following updates to HWSEQ:
- a new HWSEQ mode - Random Region Access (RRA).
- increased HWSEQ RAM size of 2KB.
Add code to support these changes.
Jira PVAAS-13252
Change-Id: I92d65524b526eda1be8f8dc81dc4e41d0db7f488
Signed-off-by: abhinayaa <abhinayaa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/2926761
Reviewed-by: Sreehari Mohan <sreeharim@nvidia.com>
Reviewed-by: Amruta Sai Anusha Bhamidipati <abhamidipati@nvidia.com>
Reviewed-by: Omar Nemri <onemri@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
