The constants defined in dla_t19x_fw_version.h have UL suffix which
translates to 64 bit unsigned integer on 64 bit architectures and 32
bit unsigned integers on 32 bit architectures such as falcon.
To be MISRA rule 10.3 compliant on both, use explicit typecast to
uint32_t which should work across both.
This change does not fix any violations in here but reflects an
update to this file that helps fix 10.3 violation in QNX KMD.
Change-Id: I18102f037f15568954dfe47467e20058308b0405
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2367282
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
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This issue mostly seen in T210 when resource policy for modules are set to
RESOURCE_PER_DEVICE and test with kernel_submit regression, Then it generally
leads to a crash in second or forthcoming iteration of kernel_submit.
Observation:
After completion of channel's job, module gets suspended without freeing the
channel, And when module resume, it's start submiting job on the channel's
syncpoint which is already freed by others.
This scenario occurs in two cases with VIC module,
1 A user application(Ex: nvgpu) freed the syncpoint and VIC module is
in suspend, Now when module will resume it will expect same syncpt
active and belongs to it.
2 In between of 1st possibility If other module(Ex: nvenc) gets the
syncpoint from free list when the first module(VIC) is suspended,
Now when first module(VIC) resume and start submiting job on the same
syncpoint which is already acquired by other module.
Changes made :
o Now, Channel will be freed on channel dma completion
o Channel will be re-acquire on every submit
o Syncpoint will not be freed when channel gets free.
o Syncpoint will be acquire once by user space and will be
freed when use space release the device
o Now, Syncpoints gets mark used and unused using chid
o Set resource policy to RESOURCE_PER_DEVICE for msenc, nvdec,
nvjpg and vic
Bug 200582662
Change-Id: Ief7658974cbd958f883e7b83add5902f766826df
Signed-off-by: Ankit Patel <anpatel@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2352726
(cherry picked from commit 745c3c8d46c23353a81e5e6035af3ed3848b02eb)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2366098
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To allow building nvhost as a module, clean up the Makefile,
Kconfig and config symbol references:
* Add most stuff into the nvhost-y/m object list, rather
than having separate targets.
* Make Kconfig symbols that are not the root GRHOST symbol
bool rather than tristate.
* Update most references to config symbols to use
IS_ENABLED rather than defined.
* While at it, make pre-T234 support be built in always.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Change-Id: I9eded315067239da7dfd3677a69e7b707cfdc127
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2363201
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- update DLA1 FW version for multichip support
- include DLA2 driver's build path
- For firmware verification with multi-chip support,
- Need to get way to distinuguish chip.
- Use tegra_get_chip_id() is not recommended practice
- Alternately, using nvhost_device_data's "version" param which distinguishes
chip specific data at compile time
- So encode fw version into "version" param
- include firmware version header to encode
- Inline function can't be used at compile to encode "version" param
through macro
Jira DLA-3182
Change-Id: Id958133739acba583690b9fdf440fa1729b2b51e
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2359966
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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- Adds DLA2 firmware version interface for version
verification
- Include DLA driver's t23x build path
- For firmware verification with multi-chip support,
- Use nvhost_device_data's "version" param which distinguishes
chip specific data at compile time
- So encode fw version into "version" param.
- Inline function can't be used at compile so use available macro
Jira DLA-3182
Change-Id: Id9185c98ae924faea7a16d5f88d30c9b183c94f2
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2359968
Reviewed-by: Praveen K <kpraveen@nvidia.com>
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Modified the commit e4163dbef1719b52b2d04782778767d313f37cdc
After installing the user space headers using make headers_install,
We do not have an uapi as a top level directory. Hence we must
include from the regular path linux|media|misc|video within the user
space header files.
Bug 2806057
Change-Id: I2f32a32814ac5347769177428717da7e7098147d
Signed-off-by: Ankit Patel <anpatel@nvidia.com>
(cherry picked from commit f8c05a422c4f14114c762906e24f4221a7343469)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2294559
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Currently,
- On device node close, nvhost ACM updates clock rate
to default rate.
- DLA default rate is set to UINT_MAX.
- These causes max rate requests from DLA on device node close.
Fix,
- Set default rate for DLA as zero. On device node close, aggregrate
requests capped.
- On device node open, keep EMC requests to max.
so DLA inference doesn't impact for perf.
Bug 2769574
Change-Id: Icdaa8943ee143a5fa8c7310db9b7fac636c5be50
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Signed-off-by: nmalwade <nmalwade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255718
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[1] Adds sof_task_status field which is written before
start of task execution. (i.e before SOF signals)
[2] eof_task_status feature already exists in form of
output_task_status (field renamed for clarity)
Jira DLA-1992
Jira DLA-1993
Change-Id: Icc26a7a40f18bb2af1caaff054641c45b9772945
Signed-off-by: Arvind M <am@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121531
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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[1] Adds support for prefence signal support
[2] Facilitates handling of SOF feature request from higher
levels
[3] Update ioctl structure for emu_submit to allow prefence
with signal action
Jira DLA-1992
Jira DLA-1993
Change-Id: Id0fe8a7a3ff46227121ec5342197b1da2a3f346d
Signed-off-by: Arvind M <am@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121530
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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[1] Action op code macros has been renamed for better
representation
[2] It has been categorized based on control (ACTION_TERMINATE),
read (ACTION_*_[GE|EQ]) and write actions (ACTION_WRITE_*)
[3] Extract different functions from nvdla_fill_preactions and
nvdla_fill_postactions
- nvdla_fill_wait_fence_action
- nvdla_fill_signal_fence_action
- nvdla_fill_taskstatus_read_action
- nvdla_fill_taskstatus_write_action
This is useful if some functions are used by both fill_preactions
and fill_postactions
Jira DLA-2027
Change-Id: Iddac852cee7d491be18982c97f930401dd41f855
Signed-off-by: Arvind M <am@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121529
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Since all of MAX_NUM_NVDLA_PREFENCES, MAX_NUM_NVDLA_POSTFENCES,
MAX_NUM_NVDLA_IN_TASK_STATUS and MAX_NUM_NVDLA_OUT_TASK_STATUS are 32,
it is possible to use narrower 'u8' type for appropriate counters.
This is similar to what we have in PVA and also fixes some annoying
warnings issued by automatic validators.
Signed-off-by: Dmitry Antipov <dantipov@nvidia.com>
Change-Id: Ia99ecb7daed7b60336254b18acaab31fab157ad4
Reviewed-on: https://git-master.nvidia.com/r/1980368
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
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For NSys, we're interested in having detailed information on what task
waits on a particular prefence or requests a particular postfence.
This is implemented by adding two extra fields, 'task_syncpt_id' and
'task_syncpt_thresh' to 'struct nvhost_task_fence', to record the task
this particular fence is associated with.
To avoid race conditon in pva_submit (similar to what was fixed in
0c2065fd669926536f79fd9e8ec33f33cbdcae2e), PVA task memory management
is changed to use simple kref-based scheme, much like it's done in DLA.
Finally, this patch renames syncpoint fields of 'task_fence' to 'syncpt_id'
and 'syncpt_thresh' to match the same field names in other events, which
is intended to simplify Python scripting.
JIRA DTSP-1662
JIRA DTSP-682
Signed-off-by: Dmitry Antipov <dantipov@nvidia.com>
Change-Id: I4c55efcae15eb80a0d950882d6ff6e5ac706ab20
Reviewed-on: https://git-master.nvidia.com/r/1978175
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
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This reverts commit c49670d23c368245670556b54ff83cc6b4edb96b.
The original commit was reverted because it exposed DLA UMD driver to
include kernel headers directly.
Since then, DLA UMD driver has been fixed to use headers from
user-space code. And hence restore this commit.
Bug 200471393
Change-Id: I221f56c5d12bd3db79568398a95baa61ffcd8101
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1980599
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This is causing Android builds to fail
This reverts commit 965ceca35c92eba011163f4c637b3b9e0f073f1a.
Change-Id: I84a98d129d25e33d1828033ab48a60102252b516
Signed-off-by: Sharif Inamdar <isharif@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959908
- Xavier has different SKUs based on which different engines are enabled
or disabled based on fuse setttings.
- This patch probes engines only if they are actually enabled in SKU by
reading SKU INFO.
- This makes sure that we dont access engines if they are enabled
inadvertently in DT
Bug 200428527
JIRA VFND-5075
Change-Id: I4d3a4c84452237fdab0426980282cd9c39cc2a28
Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1784306
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Damian Halas <dhalas@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Reviewed-by: Nirav Patel <nipatel@nvidia.com>
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