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Add a few microseconds delay between IVC channel reset retries. This prevents kernel logs from flooding if dce bootstrapping takes some time for any reason. Based on logs below, DCE is taking around 10-30 microsecond for channel reset. So, Keeping the delay of 10-20 microseconds. 20:26:46.637409: dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x5] 20:26:46.637421: message repeated 15 times: [ dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x5]] --- 20:26:46.637429: dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x1] 20:26:46.637458: message repeated 12 times: [ dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x1]] ---- 20:26:46.637461: dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x2] 20:26:46.637471: message repeated 15 times: [ dce: dce_mailbox_set_full_interrupt:157 Intr bit set multiple times for MB : [0x2]] Jira TDS-6381 Change-Id: I0f8d3c55058019df5a52edd232eae93b3bf84276 Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3304216 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
15 KiB
15 KiB