gpu: nvgpu: Move remaining GMMU HAL code to hal/mm/gmmu/

Move the remaining GMMU HAL related code from the gm20b/, gp10b/,
and gv11b/ directories to new gmmu hal source files.

Also update all makefiles and HAL init code to refelct the new
location of the headers and source code.

JIRA NVGPU-2042

Change-Id: Ic9b85cc547bd0f994ad11042fc4093c517327399
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103672
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2019-04-23 13:34:30 -07:00
committed by mobile promotions
parent 074e5fed29
commit 00d7b53b73
27 changed files with 607 additions and 408 deletions

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@@ -32,8 +32,9 @@
#include "common/mm/allocators/buddy_allocator_priv.h"
#include <gp10b/mm_gp10b.h>
#include <hal/bus/bus_gk20a.h>
#include <hal/mm/gmmu/gmmu_gp10b.h>
#include <nvgpu/hw/gk20a/hw_pram_gk20a.h>
#define SZ_8K (SZ_4K << 1)

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@@ -35,19 +35,19 @@
#include <os/posix/os_posix.h>
#include <nvgpu/posix/posix-fault-injection.h>
#include <gk20a/mm_gk20a.h>
#include <gm20b/mm_gm20b.h>
#include <gp10b/mm_gp10b.h>
#include <gv11b/mm_gv11b.h>
#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
#include <hal/mm/cache/flush_gk20a.h>
#include <hal/mm/cache/flush_gv11b.h>
#include <hal/mm/gmmu/gmmu_gp10b.h>
#include <hal/mm/gmmu/gmmu_gv11b.h>
#include <hal/fb/fb_gp10b.h>
#include <hal/fb/fb_gm20b.h>
#include <hal/fifo/ramin_gk20a.h>
#include <hal/fifo/ramin_gp10b.h>
#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
#define TEST_PA_ADDRESS 0xEFAD80000000
#define TEST_GPU_VA 0x102040600000
#define TEST_PA_ADDRESS_64K 0x1FAD80010000

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@@ -36,7 +36,7 @@
#include "common/mm/gmmu/pd_cache_priv.h"
#include "gp10b/mm_gp10b.h"
#include "hal/mm/gmmu/gmmu_gp10b.h"
/*
* Direct allocs are allocs large enough to just pass straight on to the

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@@ -35,8 +35,9 @@
#include <nvgpu/posix/posix-fault-injection.h>
#include <os/posix/os_posix.h>
#include <gp10b/mm_gp10b.h>
#include <hal/mm/gmmu/gmmu_gp10b.h>
#include <hal/bus/bus_gk20a.h>
#include <nvgpu/hw/gk20a/hw_pram_gk20a.h>
#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>

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@@ -35,16 +35,13 @@
#include <nvgpu/nvgpu_sgt.h>
#include <nvgpu/fifo.h>
#include "os/posix/os_posix.h"
#include "gk20a/mm_gk20a.h"
#include "gm20b/mm_gm20b.h"
#include "gp10b/mm_gp10b.h"
#include "gv11b/mm_gv11b.h"
#include "common/fifo/channel_gv11b.h"
#include "nvgpu/hw/gv11b/hw_gmmu_gv11b.h"
#include "nvgpu/hw/gv11b/hw_fb_gv11b.h"
#include "hal/mm/cache/flush_gk20a.h"
#include "hal/mm/cache/flush_gv11b.h"
#include "hal/mm/gmmu/gmmu_gp10b.h"
#include "hal/mm/gmmu/gmmu_gv11b.h"
#include "hal/mc/mc_gv11b.h"
#include "hal/fb/fb_gp10b.h"
#include "hal/fb/fb_gm20b.h"
@@ -54,6 +51,9 @@
#include "hal/fifo/ramin_gm20b.h"
#include "hal/fifo/ramin_gp10b.h"
#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
#include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
#define TEST_PA_ADDRESS 0xEFAD80000000
#define TEST_COMP_TAG 0xEF
#define TEST_INVALID_ADDRESS 0xAAC0000000

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@@ -35,9 +35,11 @@
#include <gp10b/mm_gp10b.h>
#include <hal/mm/cache/flush_gk20a.h>
#include <hal/mm/cache/flush_gv11b.h>
#include <hal/mm/gmmu/gmmu_gp10b.h>
#include <hal/mm/gmmu/gmmu_gv11b.h>
#include <hal/fb/fb_gp10b.h>
#include <hal/fb/fb_gm20b.h>
#include <gv11b/mm_gv11b.h>
#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
/* Random CPU physical address for the buffers we'll map */