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gpu: nvgpu: disable unused compute sw method for safety

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Add missing check with CONFIG_NVGPU_HAL_NON_FUSA in tu10x
code for NVC0C0_SET_SHADER_EXCEPTIONS.

Jira NVGPU-4454

Change-Id: Id8f0560c5061f7c017c84361059007d936dc53b5
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2257034
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vinodg
2019-12-06 11:06:19 -08:00
committed by Alex Waterman
parent 23bbce1102
commit 01039aec35
2 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
View File

@@ -69,9 +69,11 @@ int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
if (class_num == TURING_COMPUTE_A) {
switch (offset << 2) {
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
case NVC5C0_SET_SHADER_EXCEPTIONS:
g->ops.gr.intr.set_shader_exceptions(g, data);
break;
#endif
case NVC5C0_SET_SKEDCHECK:
gv11b_gr_intr_set_skedcheck(g, data);
break;

4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -661,8 +661,6 @@ static const struct gpu_ops tu104_ops = {
.intr = {
.handle_fecs_error = gv11b_gr_intr_handle_fecs_error,
.handle_sw_method = tu104_gr_intr_handle_sw_method,
.set_shader_exceptions =
gv11b_gr_intr_set_shader_exceptions,
.handle_class_error =
gm20b_gr_intr_handle_class_error,
.clear_pending_interrupts =
@@ -722,6 +720,8 @@ static const struct gpu_ops tu104_ops = {
.get_sm_no_lock_down_hww_global_esr_mask =
gv11b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask,
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
.set_shader_exceptions =
gv11b_gr_intr_set_shader_exceptions,
.tpc_exception_sm_enable =
gm20b_gr_intr_tpc_exception_sm_enable,
#endif