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gpu: nvgpu: Boardobj lite unit refactor

Browse Source 
As boardobj unit is used only in PMU, the plan is to move
all the boardobj related functions/structures and Macros
to boardobj specific folders. This will remove unnecessary
usage of boardobj outside PMU.

NVGPU-4484

Change-Id: I9f0fda32e6affd1fce218eb0ac638a9dfc8b99c3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335986
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
rmylavarapu
2020-04-29 11:57:06 +05:30
committed by Alex Waterman
parent 5f0fdf085c
commit 0115c26f1b
36 changed files with 123 additions and 158 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
arch/nvgpu-common.yaml
View File

@@ -653,8 +653,7 @@ pmu:
owner: Sagar K
# Subset of each interfaces should be distributed to individual units.
# TODO!
sources: [ include/nvgpu/pmu/pmuif/ctrlboardobj.h,
include/nvgpu/pmu/pmuif/ctrlpmgr.h,
sources: [ include/nvgpu/pmu/pmuif/ctrlpmgr.h,
include/nvgpu/pmu/pmuif/acr.h,
include/nvgpu/pmu/pmuif/ap.h,
include/nvgpu/pmu/pmuif/cmn.h,
@@ -663,7 +662,6 @@ pmu:
include/nvgpu/pmu/pmuif/pg_rppg.h,
include/nvgpu/pmu/pmuif/init.h,
include/nvgpu/pmu/pmuif/bios.h,
include/nvgpu/pmu/pmuif/boardobj.h,
include/nvgpu/pmu/pmuif/pmgr.h,
include/nvgpu/pmu/pmuif/seq.h,
include/nvgpu/pmu/pmuif/rpc.h,
@@ -676,7 +674,8 @@ pmu:
safe: yes
gpu: dgpu
sources: [ common/pmu/boardobj/boardobj.c,
include/nvgpu/boardobj.h ]
common/pmu/boardobj/boardobj.h,
common/pmu/boardobj/ucode_boardobj_inf.h ]
boardobjgrp:
safe: yes
gpu: dgpu

5
drivers/gpu/nvgpu/common/pmu/boardobj/boardobj.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,7 +22,8 @@
#include <nvgpu/kmem.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/boardobj.h>
#include "boardobj.h"
/*
* Destructor for the base board object. Called by each device-Specific

15
drivers/gpu/nvgpu/include/nvgpu/boardobj.h → drivers/gpu/nvgpu/common/pmu/boardobj/boardobj.h
View File

@@ -23,14 +23,10 @@
#ifndef NVGPU_BOARDOBJ_H
#define NVGPU_BOARDOBJ_H
#include <nvgpu/list.h>
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
#include <nvgpu/pmu/pmuif/boardobj.h>
struct boardobj;
struct nvgpu_list_node;
struct gk20a;
struct nv_pmu_boardobj;
/*
* Fills out the appropriate the nv_pmu_xxxx_device_desc_<xyz> driver->PMU
@@ -74,15 +70,6 @@ struct boardobj {
struct nvgpu_list_node node;
};
struct boardobjgrp_pmucmdhandler_params {
/* Pointer to the BOARDOBJGRP associated with this CMD */
struct boardobjgrp *pboardobjgrp;
/* Pointer to structure representing this NV_PMU_BOARDOBJ_CMD_GRP */
struct boardobjgrp_pmu_cmd *pcmd;
/* Boolean indicating whether the PMU successfully handled the CMD */
u32 success;
};
#define BOARDOBJ_GET_TYPE(pobj) (((struct boardobj *)(void *)(pobj))->type)
#define BOARDOBJ_GET_IDX(pobj) (((struct boardobj *)(void *)(pobj))->idx)

3
drivers/gpu/nvgpu/common/pmu/boardobj/boardobjgrp.c
View File

@@ -22,11 +22,12 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/pmu/cmd.h>
#include <nvgpu/pmu/super_surface.h>
#include <nvgpu/pmu/allocator.h>
#include "boardobj.h"
static int check_boardobjgrp_param(struct gk20a *g,
struct boardobjgrp *pboardobjgrp)
{

4
drivers/gpu/nvgpu/common/pmu/boardobj/boardobjgrpmask.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrpmask.h>
#include "boardobj.h"
/*
* Assures that unused bits (size .. (maskDataCount * 32 - 1)) are always zero.

66
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/boardobj.h → drivers/gpu/nvgpu/common/pmu/boardobj/ucode_boardobj_inf.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -23,8 +23,7 @@
#define NVGPU_PMUIF_BOARDOBJ_H
#include <nvgpu/flcnif_cmn.h>
#include "ctrlboardobj.h"
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
/* board object group command id's. */
#define NV_PMU_BOARDOBJGRP_CMD_SET 0x00U
@@ -38,6 +37,67 @@
#define NV_PMU_RPC_ID_THERM_BOARD_OBJ_GRP_CMD 0x00U
#define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00U
#define CTRL_BOARDOBJGRP_TYPE_INVALID 0x00U
#define CTRL_BOARDOBJGRP_TYPE_E32 0x01U
#define CTRL_BOARDOBJGRP_TYPE_E255 0x02U
#define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS 32U
#define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS 255U
#define CTRL_BOARDOBJ_MAX_BOARD_OBJECTS \
CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
#define CTRL_BOARDOBJ_IDX_INVALID 255U
#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32U
#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit) \
((_bit) / CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE)
#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(_bit) \
((_bit) % CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE)
#define CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) \
(CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1U) + 1U)
#define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE 1U
#define CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits) \
(CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) - \
CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE)
struct ctrl_boardobj {
u8 type;
};
struct ctrl_boardobjgrp_mask {
u32 data[1];
};
struct ctrl_boardobjgrp_mask_e32 {
struct ctrl_boardobjgrp_mask super;
};
struct ctrl_boardobjgrp_mask_e255 {
struct ctrl_boardobjgrp_mask super;
u32 data_e255[7];
};
struct ctrl_boardobjgrp_super {
struct ctrl_boardobjgrp_mask obj_mask;
};
struct ctrl_boardobjgrp_e32 {
struct ctrl_boardobjgrp_mask_e32 obj_mask;
};
struct CTRL_boardobjgrp_e255 {
struct ctrl_boardobjgrp_mask_e255 obj_mask;
};
struct ctrl_boardobjgrp {
u32 obj_mask;
};
/*
* Base structure describing a BOARDOBJ for communication between Kernel and
* PMU.

1
drivers/gpu/nvgpu/common/pmu/clk/clk_domain.h
View File

@@ -23,7 +23,6 @@
#ifndef NVGPU_CLK_DOMAIN_H
#define NVGPU_CLK_DOMAIN_H
#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#define CLK_DOMAIN_BOARDOBJGRP_VERSION 0x30

1
drivers/gpu/nvgpu/common/pmu/clk/clk_prog.h
View File

@@ -23,7 +23,6 @@
#ifndef NVGPU_CLK_PROG_H
#define NVGPU_CLK_PROG_H
#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>

2
drivers/gpu/nvgpu/common/pmu/clk/clk_vin.h
View File

@@ -23,9 +23,9 @@
#ifndef NVGPU_CLK_VIN_H
#define NVGPU_CLK_VIN_H
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <common/pmu/boardobj/boardobj.h>
typedef u32 vin_device_state_load(struct gk20a *g,
struct nvgpu_clk_pmupstate *clk, struct clk_vin_device *pdev);

3
drivers/gpu/nvgpu/common/pmu/clk/ucode_clk_inf.h
View File

@@ -25,9 +25,8 @@
#include <nvgpu/flcnif_cmn.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
#include <nvgpu/pmu/pmuif/boardobj.h>
#include <nvgpu/boardobjgrp_e255.h>
#include <common/pmu/boardobj/ucode_boardobj_inf.h>
/*!
* Various types of VIN calibration that the GPU can support

2
drivers/gpu/nvgpu/common/pmu/fw/fw_ver_ops.c
View File

@@ -29,7 +29,6 @@
#include <nvgpu/enabled.h>
#include <nvgpu/utils.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/clk/clk.h>
@@ -39,6 +38,7 @@
#include <nvgpu/pmu/super_surface.h>
#include <nvgpu/pmu/fw.h>
#include <nvgpu/pmu/seq.h>
#include <common/pmu/boardobj/boardobj.h>
/* PMU F/W version */
#define APP_VERSION_TU10X 28084434U

2
drivers/gpu/nvgpu/common/pmu/perf/change_seq.c
View File

@@ -24,7 +24,6 @@
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/timers.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/perf.h>
@@ -32,6 +31,7 @@
#include <nvgpu/pmu/super_surface.h>
#include <nvgpu/pmu/pmu_pstate.h>
#include <nvgpu/pmu/perf.h>
#include <common/pmu/boardobj/boardobj.h>
#include "change_seq.h"
#include "perf.h"

2
drivers/gpu/nvgpu/common/pmu/perf/pstate.c
View File

@@ -25,13 +25,13 @@
#include <nvgpu/bios.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/pmu.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
#include <nvgpu/pmu/boardobjgrp_classes.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/perf.h>
#include <common/pmu/boardobj/boardobj.h>
#include "ucode_perf_pstate_inf.h"
#include "pstate.h"

4
drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.h
View File

@@ -1,7 +1,7 @@
/*
* general power device structures & definitions
*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -24,10 +24,10 @@
#ifndef NVGPU_PMGR_PWRDEV_H
#define NVGPU_PMGR_PWRDEV_H
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#include <nvgpu/pmu/pmuif/ctrlpmgr.h>
#include <common/pmu/boardobj/boardobj.h>
#define PWRDEV_I2CDEV_DEVICE_INDEX_NONE (0xFF)

4
drivers/gpu/nvgpu/common/pmu/pmgr/pwrmonitor.h
View File

@@ -1,7 +1,7 @@
/*
* general power channel structures & definitions
*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -26,8 +26,8 @@
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/pmu/pmuif/ctrlpmgr.h>
#include <common/pmu/boardobj/boardobj.h>
struct pwr_channel {
struct boardobj super;

4
drivers/gpu/nvgpu/common/pmu/pmgr/pwrpolicy.h
View File

@@ -1,7 +1,7 @@
/*
* general power channel structures & definitions
*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -26,8 +26,8 @@
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/pmu/pmuif/ctrlpmgr.h>
#include <common/pmu/boardobj/boardobj.h>
#define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4U

3
drivers/gpu/nvgpu/common/pmu/pmu.c
View File

@@ -27,10 +27,11 @@
#include <nvgpu/utils.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/pmu.h>
#include "boardobj/boardobj.h"
/* PMU H/W error functions */
void nvgpu_pmu_report_bar0_pri_err_status(struct gk20a *g, u32 bar0_status,
u32 error_type)

3
drivers/gpu/nvgpu/common/pmu/pmu_pstate.c
View File

@@ -25,7 +25,6 @@
#include <nvgpu/bios.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/pmu.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
@@ -36,6 +35,8 @@
#include <nvgpu/pmu/volt.h>
#include <nvgpu/pmu/pmu_pstate.h>
#include "boardobj/boardobj.h"
void nvgpu_pmu_pstate_deinit(struct gk20a *g)
{
pmgr_pmu_free_pmupstate(g);

3
drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c
View File

@@ -27,7 +27,6 @@
#include <nvgpu/utils.h>
#include <nvgpu/power_features/cg.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp.h>
#include <nvgpu/pmu.h>
@@ -40,6 +39,8 @@
#include <nvgpu/pmu/debug.h>
#include <nvgpu/pmu/pmu_pstate.h>
#include "boardobj/boardobj.h"
#ifdef CONFIG_NVGPU_POWER_PG
#include <nvgpu/pmu/pmu_pg.h>
#endif

2
drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h
View File

@@ -24,9 +24,9 @@
#define SUPER_SURFACE_PRIV_H
#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
#include <nvgpu/pmu/pmuif/boardobj.h>
#include <nvgpu/pmu/pmuif/cmn.h>
#include <nvgpu/flcnif_cmn.h>
#include <common/pmu/boardobj/ucode_boardobj_inf.h>
struct nvgpu_mem;

2
drivers/gpu/nvgpu/common/pmu/therm/therm_channel.h
View File

@@ -24,8 +24,8 @@
#ifndef NVGPU_THERM_THRMCHANNEL_H
#define NVGPU_THERM_THRMCHANNEL_H
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <common/pmu/boardobj/boardobj.h>
struct therm_channel {
struct boardobj super;

2
drivers/gpu/nvgpu/common/pmu/therm/therm_dev.h
View File

@@ -24,8 +24,8 @@
#ifndef NVGPU_THERM_THRMDEV_H
#define NVGPU_THERM_THRMDEV_H
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <common/pmu/boardobj/boardobj.h>
struct nvgpu_pmu_therm;

3
drivers/gpu/nvgpu/common/pmu/volt/volt.h
View File

@@ -23,9 +23,8 @@
#ifndef NVGPU_VOLT_H
#define NVGPU_VOLT_H
#include <nvgpu/pmu/pmuif/boardobj.h>
#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <common/pmu/boardobj/ucode_boardobj_inf.h>
#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U

2
drivers/gpu/nvgpu/common/pmu/volt/volt_dev.h
View File

@@ -23,8 +23,8 @@
#ifndef NVGPU_VOLT_DEV_H
#define NVGPU_VOLT_DEV_H
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp.h>
#include <common/pmu/boardobj/boardobj.h>
#include "ucode_volt_inf.h"

2
drivers/gpu/nvgpu/common/pmu/volt/volt_rail.h
View File

@@ -24,8 +24,8 @@
#ifndef NVGPU_VOLT_RAIL_H
#define NVGPU_VOLT_RAIL_H
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp.h>
#include <common/pmu/boardobj/boardobj.h>
#define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFFU

10
drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h
View File

@@ -28,11 +28,18 @@ struct gk20a;
struct nvgpu_list_node;
/* ------------------------ Includes ----------------------------------------*/
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrpmask.h>
#include <nvgpu/list.h>
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/pmu/super_surface.h>
#include <nvgpu/flcnif_cmn.h>
/* Dependency of this include will be removed in further CL */
#include "../../common/pmu/boardobj/boardobj.h"
struct nv_pmu_boardobjgrp_super;
struct nv_pmu_boardobjgrp;
struct nv_pmu_boardobj;
struct nv_pmu_boardobj_query;
/*
* Board Object Group Remover and destructor. This is used to remove and
@@ -149,7 +156,6 @@ struct boardobjgrp {
int (*pmugetstatus)(struct gk20a *g,
struct boardobjgrp *pboardobjgrp,
struct boardobjgrpmask *mask);
int (*pmudatainstget)(struct gk20a *g,
struct nv_pmu_boardobjgrp *boardobjgrppmu,
struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx);

5
drivers/gpu/nvgpu/include/nvgpu/boardobjgrp_e32.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -39,7 +39,8 @@ struct boardobjgrp_e32 {
/*
* Statically allocated array of PBOARDOBJ-s
*/
struct boardobj *objects[CTRL_BOARDOBJGRP_E32_MAX_OBJECTS];
/* 32 will be replaced with CTRL_BOARDOBJGRP_E32_MAX_OBJECTS */
struct boardobj *objects[32];
/*
* Statically allocated mask strcuture referenced by super::pMask.

6
drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,7 +25,6 @@
struct ctrl_boardobjgrp_mask;
/*
* Board Object Group Mask super-structure.
* Used to unify access to all BOARDOBJGRPMASK_E** child classes
@@ -44,7 +43,8 @@ struct boardobjgrpmask {
* Start of the array of 32-bit words representing the bit-mask
* Must be the last element of the structure.
*/
u32 data[CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE];
/* 1 will be replace with CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE */
u32 data[1];
};
struct boardobjgrpmask_e32 {

4
drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
View File

@@ -35,10 +35,12 @@ struct gk20a;
#include <nvgpu/log.h>
#include <nvgpu/barrier.h>
#include <nvgpu/cond.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/pmu/volt.h>
/* Dependency of this include will be removed in further CL */
#include "../../common/pmu/boardobj/boardobj.h"
#define MAX_F_POINTS 256
#define DEFAULT_EVENT_NUMBER 32U

4
drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk.h
View File

@@ -26,10 +26,12 @@
#define NVGPU_PMU_CLK_H
#include <nvgpu/types.h>
#include <nvgpu/pmu/pmuif/ctrlboardobj.h>
#include <nvgpu/boardobjgrpmask.h>
#include <nvgpu/boardobjgrp_e32.h>
/* Following include will be removed in further CL */
#include "../../../../common/pmu/boardobj/ucode_boardobj_inf.h"
/*!
* Valid global VIN ID values
*/

1
drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h
View File

@@ -26,7 +26,6 @@
#include <nvgpu/pmu/pmuif/perfmon.h>
#include <nvgpu/pmu/pmuif/pg.h>
#include <nvgpu/pmu/pmuif/acr.h>
#include <nvgpu/pmu/pmuif/boardobj.h>
#include <nvgpu/pmu/pmuif/pmgr.h>
#include <nvgpu/pmu/pmuif/rpc.h>

1
drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h
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@@ -28,7 +28,6 @@
#include <nvgpu/pmu/pmuif/perfmon.h>
#include <nvgpu/pmu/pmuif/acr.h>
#include <nvgpu/pmu/pmuif/rpc.h>
#include <nvgpu/pmu/pmuif/boardobj.h>
#include <nvgpu/pmu/pmuif/pmgr.h>
/* GPU ID */

91
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlboardobj.h
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@@ -1,91 +0,0 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_PMUIF_CTRLBOARDOBJ_H
#define NVGPU_PMUIF_CTRLBOARDOBJ_H
#include <nvgpu/types.h>
struct ctrl_boardobj {
u8 type;
};
#define CTRL_BOARDOBJGRP_TYPE_INVALID 0x00U
#define CTRL_BOARDOBJGRP_TYPE_E32 0x01U
#define CTRL_BOARDOBJGRP_TYPE_E255 0x02U
#define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS 32U
#define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS 255U
#define CTRL_BOARDOBJ_MAX_BOARD_OBJECTS \
CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
#define CTRL_BOARDOBJ_IDX_INVALID 255U
#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32U
#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit) \
((_bit) / CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE)
#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(_bit) \
((_bit) % CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE)
#define CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) \
(CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1U) + 1U)
#define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE 1U
#define CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits) \
(CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) - \
CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE)
struct ctrl_boardobjgrp_mask {
u32 data[1];
};
struct ctrl_boardobjgrp_mask_e32 {
struct ctrl_boardobjgrp_mask super;
};
struct ctrl_boardobjgrp_mask_e255 {
struct ctrl_boardobjgrp_mask super;
u32 data_e255[7];
};
struct ctrl_boardobjgrp_super {
struct ctrl_boardobjgrp_mask obj_mask;
};
struct ctrl_boardobjgrp_e32 {
struct ctrl_boardobjgrp_mask_e32 obj_mask;
};
struct CTRL_boardobjgrp_e255 {
struct ctrl_boardobjgrp_mask_e255 obj_mask;
};
struct ctrl_boardobjgrp {
u32 obj_mask;
};
#endif /* NVGPU_PMUIF_CTRLBOARDOBJ_H */

4
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlpmgr.h
View File

@@ -1,7 +1,7 @@
/*
* Control pmgr state infrastructure
*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -24,8 +24,6 @@
#ifndef NVGPU_PMUIF_CTRLPMGR_H
#define NVGPU_PMUIF_CTRLPMGR_H
#include "ctrlboardobj.h"
/* valid power domain values */
#define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES 32U
#define CTRL_PMGR_PWR_VIOLATION_MAX 0x06U

4
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/pmgr.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -24,9 +24,9 @@
#define NVGPU_PMUIF_PMGR_H
#include <nvgpu/flcnif_cmn.h>
#include "../../../../common/pmu/boardobj/ucode_boardobj_inf.h"
#include "ctrlpmgr.h"
#include "boardobj.h"
struct nv_pmu_pmgr_i2c_device_desc {
struct nv_pmu_boardobj super;

4
drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
View File

@@ -19,12 +19,14 @@
#include "os_linux.h"
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
#include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/volt.h>
/* Dependency of this include will be removed in further CL */
#include "../../common/pmu/boardobj/boardobj.h"
#include "hal/clk/clk_tu104.h"
void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);