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gpu: nvgpu: add gr gops to enable/handle zrop/crop/rrh hww

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Add the following gr gops functions:
- enable_gpc_crop_hww
- enable_gpc_zrop_hww
- handle_gpc_crop_hww
- handle_gpc_zrop_hww
- handle_gpc_rrh_hww

These gr gops will be used in nvgpu-next.

Add function: nvgpu_gr_rop_offset to compute rop pri offsets.

Jira: NVGPU-5237

Change-Id: I9e2437c1d2893238b16ec7a134543e20c81b49f7
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335687
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2020-04-28 20:59:53 +05:30
committed by Alex Waterman
parent 8e49ea4e71
commit 077a07ff9f
4 changed files with 47 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/nvgpu/common/gr/gr.c
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@@ -145,13 +145,20 @@ u32 nvgpu_gr_tpc_offset(struct gk20a *g, u32 tpc)
u32 nvgpu_gr_sm_offset(struct gk20a *g, u32 sm)
{
u32 sm_pri_stride = nvgpu_get_litter_value(g, GPU_LIT_SM_PRI_STRIDE);
u32 sm_offset = nvgpu_safe_mult_u32(sm_pri_stride, sm);
return sm_offset;
}
u32 nvgpu_gr_rop_offset(struct gk20a *g, u32 rop)
{
u32 rop_pri_stride = nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE);
u32 rop_offset = nvgpu_safe_mult_u32(rop_pri_stride, rop);
return rop_offset;
}
void nvgpu_gr_init(struct gk20a *g)
{
(void)nvgpu_cond_init(&g->gr->init_wq);

18
drivers/gpu/nvgpu/common/gr/gr_intr.c
View File

@@ -705,6 +705,24 @@ int nvgpu_gr_intr_handle_gpc_exception(struct gk20a *g, bool *post_event,
gpc_exception);
}
/* Handle ZROP exception */
if (g->ops.gr.intr.handle_gpc_zrop_hww != NULL) {
g->ops.gr.intr.handle_gpc_zrop_hww(g, gpc,
gpc_exception);
}
/* Handle CROP exception */
if (g->ops.gr.intr.handle_gpc_crop_hww != NULL) {
g->ops.gr.intr.handle_gpc_crop_hww(g, gpc,
gpc_exception);
}
/* Handle RRH exception */
if (g->ops.gr.intr.handle_gpc_rrh_hww != NULL) {
g->ops.gr.intr.handle_gpc_rrh_hww(g, gpc,
gpc_exception);
}
}
return ret;

8
drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
View File

@@ -457,6 +457,12 @@ struct gops_gr_intr {
struct nvgpu_gr_isr_data *isr_data);
void (*handle_notify_pending)(struct gk20a *g,
struct nvgpu_gr_isr_data *isr_data);
void (*handle_gpc_zrop_hww)(struct gk20a *g, u32 gpc,
u32 gpc_exception);
void (*handle_gpc_crop_hww)(struct gk20a *g, u32 gpc,
u32 gpc_exception);
void (*handle_gpc_rrh_hww)(struct gk20a *g, u32 gpc,
u32 gpc_exception);
void (*handle_gcc_exception)(struct gk20a *g, u32 gpc,
u32 gpc_exception,
u32 *corrected_err, u32 *uncorrected_err);
@@ -485,6 +491,8 @@ struct gops_gr_intr {
void (*enable_exceptions)(struct gk20a *g,
struct nvgpu_gr_config *gr_config,
bool enable);
void (*enable_gpc_crop_hww)(struct gk20a *g);
void (*enable_gpc_zrop_hww)(struct gk20a *g);
void (*enable_gpc_exceptions)(struct gk20a *g,
struct nvgpu_gr_config *gr_config);
void (*tpc_exception_sm_enable)(struct gk20a *g);

13
drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
View File

@@ -318,6 +318,19 @@ u32 nvgpu_gr_tpc_offset(struct gk20a *g, u32 tpc);
*/
u32 nvgpu_gr_sm_offset(struct gk20a *g, u32 sm);
/**
* @brief Get pri base register offset of a given ROP instance within a GPC
*
* @param g [in] Pointer to GPU driver struct.
* @param rop [in] ROP index.
*
* This function calculates and returns base register offset of a given
* ROP within a GPC.
*
* @return base register offset of a given ROP.
*/
u32 nvgpu_gr_rop_offset(struct gk20a *g, u32 rop);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
/**
* @brief Wait for GR engine to be initialized