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gpu: nvgpu: boardobj: fix MISRA 10.3 issues

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MISRA Rule 10.3 prohibits implicit assignment to different essential or
narrower types. This fixes a number of MISRA 10.3 violations in
common/boardobj.

JIRA NVGPU-2956

Change-Id: I3ad2376b5f61607693b3c553dce09d6ced429374
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077495
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-03-18 16:25:22 -04:00
committed by mobile promotions
parent e2fe43fd42
commit 0bf1e8773b
3 changed files with 10 additions and 7 deletions
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6
drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c
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@@ -236,7 +236,7 @@ int boardobjgrpmask_bitclr(struct boardobjgrpmask *mask, u8 bitidx)
index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
mask->data[index] &= ~BIT(offset);
mask->data[index] &= ~BIT32(offset);
return 0;
}
@@ -256,7 +256,7 @@ int boardobjgrpmask_bitset(struct boardobjgrpmask *mask, u8 bitidx)
index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
mask->data[index] |= BIT(offset);
mask->data[index] |= BIT32(offset);
return 0;
}
@@ -276,7 +276,7 @@ int boardobjgrpmask_bitinv(struct boardobjgrpmask *mask, u8 bitidx)
index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
mask->data[index] ^= ~BIT(offset);
mask->data[index] ^= ~BIT32(offset);
return 0;
}