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gpu: nvgpu: disable access to regs in MIG mode

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The following registers belong to GR but are not a part of
Sys-Compute Pipe.

gr_pd_num_tpc_per_gpc_r
gr_ds_num_tpc_per_gpc_r

Jira NVGPU-6699

Change-Id: I350b0ea429f98845db4a31168a8dfb9211706c7a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521784
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Debarshi Dutta
2021-04-28 17:50:40 +05:30
committed by mobile promotions
parent c78efae5e7
commit 0d5bcdf28b
1 changed files with 4 additions and 2 deletions
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6
drivers/gpu/nvgpu/common/gr/fs_state.c
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -143,7 +143,9 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
config, NULL, false);
}
g->ops.gr.init.pd_tpc_per_gpc(g, config);
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
g->ops.gr.init.pd_tpc_per_gpc(g, config);
}
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {