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git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-24 10:34:43 +03:00
gpu: nvgpu: Implement own rail gating code
Move rail gating sequence to happen in nvgpu driver instead of piggybacking on Tegra power gating APIs. Bug 200115454 Change-Id: I8514686c7b137f200021b05ead7157d0883bddc5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/761991
This commit is contained in:
Terje Bergstrom
@@ -175,6 +175,7 @@ struct gk20a_platform {
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int (*reset_assert)(struct platform_device *pdev);
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int (*reset_deassert)(struct platform_device *pdev);
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struct clk *clk_reset;
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struct dvfs_rail *gpu_rail;
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bool virtual_dev;
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#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
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@@ -20,13 +20,16 @@
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#include <linux/debugfs.h>
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#include <linux/tegra-powergate.h>
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#include <linux/platform_data/tegra_edp.h>
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#include <linux/delay.h>
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#include <uapi/linux/nvgpu.h>
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#include <linux/dma-buf.h>
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#include <linux/nvmap.h>
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#include <linux/tegra_pm_domains.h>
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#include <linux/tegra_soctherm.h>
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#include <linux/platform/tegra/clock.h>
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#include <linux/platform/tegra/dvfs.h>
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#include <linux/platform/tegra/common.h>
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#include <linux/platform/tegra/mc.h>
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#include <linux/clk/tegra.h>
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#include <linux/platform/tegra/tegra_emc.h>
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@@ -40,6 +43,8 @@
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#define TEGRA_GM20B_BW_PER_FREQ 64
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#define TEGRA_DDR3_BW_PER_FREQ 16
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#define TEGRA_DDR4_BW_PER_FREQ 16
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#define MC_CLIENT_GPU 34
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#define PMC_GPU_RG_CNTRL_0 0x2d4
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extern struct device tegra_vpr_dev;
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@@ -48,6 +53,16 @@ struct gk20a_emc_params {
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long freq_last_set;
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};
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static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
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static inline u32 pmc_read(unsigned long reg)
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{
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return readl(pmc + reg);
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}
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static inline void pmc_write(u32 val, unsigned long reg)
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{
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writel_relaxed(val, pmc + reg);
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}
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#define MHZ_TO_HZ(x) ((x) * 1000000)
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#define HZ_TO_MHZ(x) ((x) / 1000000)
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@@ -283,6 +298,7 @@ static void gk20a_tegra_calibrate_emc(struct platform_device *pdev,
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emc_params->bw_ratio = (gpu_bw / emc_bw);
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}
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#ifdef CONFIG_TEGRA_CLK_FRAMEWORK
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/*
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* gk20a_tegra_is_railgated()
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*
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@@ -291,10 +307,11 @@ static void gk20a_tegra_calibrate_emc(struct platform_device *pdev,
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static bool gk20a_tegra_is_railgated(struct platform_device *pdev)
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{
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struct gk20a_platform *platform = platform_get_drvdata(pdev);
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bool ret = false;
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if (!tegra_platform_is_linsim())
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ret = !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU);
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ret = !tegra_dvfs_is_rail_up(platform->gpu_rail);
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return ret;
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}
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@@ -307,10 +324,103 @@ static bool gk20a_tegra_is_railgated(struct platform_device *pdev)
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static int gk20a_tegra_railgate(struct platform_device *pdev)
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{
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if (!tegra_platform_is_linsim() &&
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tegra_powergate_is_powered(TEGRA_POWERGATE_GPU))
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tegra_powergate_partition(TEGRA_POWERGATE_GPU);
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struct gk20a_platform *platform = platform_get_drvdata(pdev);
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int ret = 0;
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if (tegra_platform_is_linsim() ||
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!tegra_dvfs_is_rail_up(platform->gpu_rail))
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return 0;
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tegra_mc_flush(MC_CLIENT_GPU);
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udelay(10);
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/* enable clamp */
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pmc_write(0x1, PMC_GPU_RG_CNTRL_0);
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pmc_read(PMC_GPU_RG_CNTRL_0);
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udelay(10);
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platform->reset_assert(pdev);
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udelay(10);
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/*
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* GPCPLL is already disabled before entering this function; reference
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* clocks are enabled until now - disable them just before rail gating
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*/
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clk_disable(platform->clk[0]);
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clk_disable(platform->clk[1]);
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udelay(10);
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if (tegra_dvfs_is_rail_up(platform->gpu_rail)) {
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ret = tegra_dvfs_rail_power_down(platform->gpu_rail);
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if (ret)
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goto err_power_off;
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} else
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pr_info("No GPU regulator?\n");
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return 0;
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err_power_off:
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gk20a_err(&pdev->dev, "Could not railgate GPU");
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return ret;
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}
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/*
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* gm20b_tegra_railgate()
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*
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* Gate (disable) gm20b power rail
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*/
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static int gm20b_tegra_railgate(struct platform_device *pdev)
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{
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struct gk20a_platform *platform = platform_get_drvdata(pdev);
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int ret = 0;
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if (tegra_platform_is_linsim() ||
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!tegra_dvfs_is_rail_up(platform->gpu_rail))
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return 0;
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tegra_mc_flush(MC_CLIENT_GPU);
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udelay(10);
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/* enable clamp */
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pmc_write(0x1, PMC_GPU_RG_CNTRL_0);
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pmc_read(PMC_GPU_RG_CNTRL_0);
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udelay(10);
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platform->reset_assert(pdev);
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udelay(10);
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/*
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* GPCPLL is already disabled before entering this function; reference
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* clocks are enabled until now - disable them just before rail gating
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*/
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clk_disable(platform->clk_reset);
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clk_disable(platform->clk[0]);
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clk_disable(platform->clk[1]);
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udelay(10);
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tegra_soctherm_gpu_tsens_invalidate(1);
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if (tegra_dvfs_is_rail_up(platform->gpu_rail)) {
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ret = tegra_dvfs_rail_power_down(platform->gpu_rail);
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if (ret)
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goto err_power_off;
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} else
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pr_info("No GPU regulator?\n");
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return 0;
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err_power_off:
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gk20a_err(&pdev->dev, "Could not railgate GPU");
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return ret;
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}
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/*
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@@ -321,12 +431,151 @@ static int gk20a_tegra_railgate(struct platform_device *pdev)
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static int gk20a_tegra_unrailgate(struct platform_device *pdev)
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{
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struct gk20a_platform *platform = platform_get_drvdata(pdev);
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int ret = 0;
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if (!tegra_platform_is_linsim())
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ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU);
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bool first = false;
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if (tegra_platform_is_linsim())
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return 0;
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if (!platform->gpu_rail) {
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platform->gpu_rail = tegra_dvfs_get_rail_by_name("vdd_gpu");
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if (IS_ERR_OR_NULL(platform->gpu_rail)) {
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WARN(1, "No GPU regulator?\n");
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return -EINVAL;
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}
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first = true;
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}
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ret = tegra_dvfs_rail_power_up(platform->gpu_rail);
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if (ret)
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return ret;
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if (!first) {
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ret = clk_enable(platform->clk[0]);
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if (ret) {
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gk20a_err(&pdev->dev, "could not turn on gpu pll");
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goto err_clk_on;
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}
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ret = clk_enable(platform->clk[1]);
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if (ret) {
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gk20a_err(&pdev->dev, "could not turn on pwr clock");
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goto err_clk_on;
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}
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}
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udelay(10);
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platform->reset_assert(pdev);
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udelay(10);
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pmc_write(0, PMC_GPU_RG_CNTRL_0);
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pmc_read(PMC_GPU_RG_CNTRL_0);
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udelay(10);
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platform->reset_deassert(pdev);
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/* Flush MC after boot/railgate/SC7 */
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tegra_mc_flush(MC_CLIENT_GPU);
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udelay(10);
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tegra_mc_flush_done(MC_CLIENT_GPU);
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udelay(10);
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return 0;
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err_clk_on:
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tegra_dvfs_rail_power_down(platform->gpu_rail);
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return ret;
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}
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/*
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* gm20b_tegra_unrailgate()
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*
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* Ungate (enable) gm20b power rail
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*/
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static int gm20b_tegra_unrailgate(struct platform_device *pdev)
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{
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struct gk20a_platform *platform = platform_get_drvdata(pdev);
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int ret = 0;
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bool first = false;
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if (tegra_platform_is_linsim())
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return 0;
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if (!platform->gpu_rail) {
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platform->gpu_rail = tegra_dvfs_get_rail_by_name("vdd_gpu");
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if (IS_ERR_OR_NULL(platform->gpu_rail)) {
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WARN(1, "No GPU regulator?\n");
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return -EINVAL;
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}
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first = true;
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}
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ret = tegra_dvfs_rail_power_up(platform->gpu_rail);
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if (ret)
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return ret;
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tegra_soctherm_gpu_tsens_invalidate(0);
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if (!first) {
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ret = clk_enable(platform->clk_reset);
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if (ret) {
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gk20a_err(&pdev->dev, "could not turn on gpu_gate");
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goto err_clk_on;
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}
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ret = clk_enable(platform->clk[0]);
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if (ret) {
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gk20a_err(&pdev->dev, "could not turn on gpu pll");
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goto err_clk_on;
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}
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ret = clk_enable(platform->clk[1]);
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if (ret) {
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gk20a_err(&pdev->dev, "could not turn on pwr clock");
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goto err_clk_on;
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}
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}
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udelay(10);
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platform->reset_assert(pdev);
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udelay(10);
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pmc_write(0, PMC_GPU_RG_CNTRL_0);
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pmc_read(PMC_GPU_RG_CNTRL_0);
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udelay(10);
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clk_disable(platform->clk_reset);
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platform->reset_deassert(pdev);
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clk_enable(platform->clk_reset);
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/* Flush MC after boot/railgate/SC7 */
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tegra_mc_flush(MC_CLIENT_GPU);
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udelay(10);
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tegra_mc_flush_done(MC_CLIENT_GPU);
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udelay(10);
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return 0;
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err_clk_on:
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tegra_dvfs_rail_power_down(platform->gpu_rail);
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return ret;
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}
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#endif
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static struct {
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char *name;
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unsigned long default_rate;
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@@ -565,9 +814,11 @@ struct gk20a_platform gk20a_tegra_platform = {
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/* power management callbacks */
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.suspend = gk20a_tegra_suspend,
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#ifdef CONFIG_TEGRA_CLK_FRAMEWORK
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.railgate = gk20a_tegra_railgate,
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.unrailgate = gk20a_tegra_unrailgate,
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.is_railgated = gk20a_tegra_is_railgated,
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#endif
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.busy = gk20a_tegra_busy,
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.idle = gk20a_tegra_idle,
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@@ -592,7 +843,6 @@ struct gk20a_platform gm20b_tegra_platform = {
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/* power management configuration */
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.railgate_delay = 500,
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.clockgate_delay = 50,
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/* Disable all power features for gm20b */
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.can_railgate = true,
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.enable_slcg = true,
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.enable_blcg = true,
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@@ -610,9 +860,11 @@ struct gk20a_platform gm20b_tegra_platform = {
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/* power management callbacks */
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.suspend = gk20a_tegra_suspend,
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.railgate = gk20a_tegra_railgate,
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.unrailgate = gk20a_tegra_unrailgate,
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#ifdef CONFIG_TEGRA_CLK_FRAMEWORK
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.railgate = gm20b_tegra_railgate,
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.unrailgate = gm20b_tegra_unrailgate,
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.is_railgated = gk20a_tegra_is_railgated,
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#endif
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.busy = gk20a_tegra_busy,
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.idle = gk20a_tegra_idle,
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