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gpu:nvgpu: vbios: fix MISRA 21.2 violations

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MISRA Rule 21.2 prohibits naming identifiers beginning with double
underscore. Rename __nvgpu_bios_readdbyte to nvgpu_bios_readbyte_impl to
comply.

JIRA NVGPU-3317

Change-Id: Ic5eaf0a629db8669c52cc6c8a2218499ceb0d8e4
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114878
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-05-08 11:28:40 -04:00
committed by mobile promotions
parent 8f1e12f4bb
commit 173f23754d
1 changed files with 9 additions and 9 deletions
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18
drivers/gpu/nvgpu/common/vbios/bios.c
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@@ -546,20 +546,20 @@ static void nvgpu_bios_parse_bit(struct gk20a *g, u32 offset)
nvgpu_log_fn(g, "done");
}
static u32 __nvgpu_bios_readbyte(struct gk20a *g, u32 offset)
static u32 nvgpu_bios_readbyte_impl(struct gk20a *g, u32 offset)
{
return g->bios.data[offset];
}
u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset)
{
return (u8)__nvgpu_bios_readbyte(g, offset);
return (u8)nvgpu_bios_readbyte_impl(g, offset);
}
s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset)
{
u32 val;
val = __nvgpu_bios_readbyte(g, offset);
val = nvgpu_bios_readbyte_impl(g, offset);
val = ((val & 0x80U) != 0U) ? (val | ~0xffU) : val;
return (s8) val;
@@ -569,8 +569,8 @@ u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset)
{
u16 val;
val = U16(__nvgpu_bios_readbyte(g, offset) |
(__nvgpu_bios_readbyte(g, offset+1U) << 8U));
val = U16(nvgpu_bios_readbyte_impl(g, offset) |
(nvgpu_bios_readbyte_impl(g, offset+1U) << 8U));
return val;
}
@@ -579,10 +579,10 @@ u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset)
{
u32 val;
val = U32(__nvgpu_bios_readbyte(g, offset) |
(__nvgpu_bios_readbyte(g, offset+1U) << 8U) |
(__nvgpu_bios_readbyte(g, offset+2U) << 16U) |
(__nvgpu_bios_readbyte(g, offset+3U) << 24U));
val = U32(nvgpu_bios_readbyte_impl(g, offset) |
(nvgpu_bios_readbyte_impl(g, offset+1U) << 8U) |
(nvgpu_bios_readbyte_impl(g, offset+2U) << 16U) |
(nvgpu_bios_readbyte_impl(g, offset+3U) << 24U));
return val;
}