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gpu:nvgpu: vbios: fix MISRA 21.2 violations
MISRA Rule 21.2 prohibits naming identifiers beginning with double underscore. Rename __nvgpu_bios_readdbyte to nvgpu_bios_readbyte_impl to comply. JIRA NVGPU-3317 Change-Id: Ic5eaf0a629db8669c52cc6c8a2218499ceb0d8e4 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2114878 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -546,20 +546,20 @@ static void nvgpu_bios_parse_bit(struct gk20a *g, u32 offset)
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nvgpu_log_fn(g, "done");
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nvgpu_log_fn(g, "done");
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}
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}
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static u32 __nvgpu_bios_readbyte(struct gk20a *g, u32 offset)
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static u32 nvgpu_bios_readbyte_impl(struct gk20a *g, u32 offset)
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{
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{
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return g->bios.data[offset];
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return g->bios.data[offset];
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}
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}
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u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset)
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u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset)
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{
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{
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return (u8)__nvgpu_bios_readbyte(g, offset);
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return (u8)nvgpu_bios_readbyte_impl(g, offset);
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}
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}
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s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset)
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s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset)
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{
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{
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u32 val;
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u32 val;
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val = __nvgpu_bios_readbyte(g, offset);
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val = nvgpu_bios_readbyte_impl(g, offset);
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val = ((val & 0x80U) != 0U) ? (val | ~0xffU) : val;
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val = ((val & 0x80U) != 0U) ? (val | ~0xffU) : val;
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return (s8) val;
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return (s8) val;
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@@ -569,8 +569,8 @@ u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset)
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{
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{
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u16 val;
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u16 val;
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val = U16(__nvgpu_bios_readbyte(g, offset) |
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val = U16(nvgpu_bios_readbyte_impl(g, offset) |
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(__nvgpu_bios_readbyte(g, offset+1U) << 8U));
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(nvgpu_bios_readbyte_impl(g, offset+1U) << 8U));
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return val;
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return val;
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}
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}
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@@ -579,10 +579,10 @@ u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset)
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{
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{
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u32 val;
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u32 val;
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val = U32(__nvgpu_bios_readbyte(g, offset) |
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val = U32(nvgpu_bios_readbyte_impl(g, offset) |
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(__nvgpu_bios_readbyte(g, offset+1U) << 8U) |
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(nvgpu_bios_readbyte_impl(g, offset+1U) << 8U) |
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(__nvgpu_bios_readbyte(g, offset+2U) << 16U) |
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(nvgpu_bios_readbyte_impl(g, offset+2U) << 16U) |
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(__nvgpu_bios_readbyte(g, offset+3U) << 24U));
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(nvgpu_bios_readbyte_impl(g, offset+3U) << 24U));
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return val;
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return val;
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}
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}
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