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gpu: nvgpu: ga10b, ga100: replace legacy pmasys control register

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Starting from Ampere+ chips, PMASYS control register layout has
been re-organized to support multiple PMA streaming channels.
In accordance with this update perf HALs to replace legacy register with
new registers.

The mapping between the legacy register and new register fields can
be found here: http://nvbugs/2332044/16.

Jira NVGPU-6906
Bug 200737354

Change-Id: I4ed5af7be04f7e2b97a8bf500de3a04cf1e4834c
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2559392
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Antony Clince Alex
2021-06-01 06:30:22 +00:00
committed by mobile promotions
parent 493df6cb6e
commit 1782bb435b
3 changed files with 25 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/nvgpu/hal/perf/perf_ga10b.c
View File

@@ -274,13 +274,13 @@ const u32 *ga10b_perf_get_hwpm_fbp_perfmon_regs(u32 *count)
bool ga10b_perf_get_membuf_overflow_status(struct gk20a *g) bool ga10b_perf_get_membuf_overflow_status(struct gk20a *g)
{ {
const u32 st = const u32 st =
perf_pmasys_channel_control_membuf_status_overflowed_f(); perf_pmasys_channel_status_secure_membuf_status_overflowed_f();
nvgpu_assert(perf_pmasys_channel_control__size_1_v() == nvgpu_assert(perf_pmasys_channel_status_secure__size_1_v() ==
pmasys_channel_instance_max_size); pmasys_channel_instance_max_size);
return st == (nvgpu_readl(g, return st == (nvgpu_readl(g,
perf_pmasys_channel_control_r(inst_zero)) & st); perf_pmasys_channel_status_secure_r(inst_zero)) & st);
} }
u32 ga10b_perf_get_membuf_pending_bytes(struct gk20a *g) u32 ga10b_perf_get_membuf_pending_bytes(struct gk20a *g)
@@ -311,7 +311,7 @@ void ga10b_perf_membuf_reset_streaming(struct gk20a *g)
u32 num_unread_bytes; u32 num_unread_bytes;
u32 i; u32 i;
nvgpu_assert(perf_pmasys_channel_control__size_1_v() == nvgpu_assert(perf_pmasys_channel_control_user__size_1_v() ==
pmasys_channel_instance_max_size); pmasys_channel_instance_max_size);
nvgpu_assert(perf_pmasys_channel_mem_bytes__size_1_v() == nvgpu_assert(perf_pmasys_channel_mem_bytes__size_1_v() ==
pmasys_channel_instance_max_size); pmasys_channel_instance_max_size);
@@ -322,9 +322,9 @@ void ga10b_perf_membuf_reset_streaming(struct gk20a *g)
WARN_ON(0U == WARN_ON(0U ==
(engine_status & perf_pmasys_enginestatus_rbufempty_empty_f())); (engine_status & perf_pmasys_enginestatus_rbufempty_empty_f()));
for (i = 0U; i < perf_pmasys_channel_control__size_1_v(); i++) { for (i = 0U; i < perf_pmasys_channel_control_user__size_1_v(); i++) {
nvgpu_writel(g, perf_pmasys_channel_control_r(i), nvgpu_writel(g, perf_pmasys_channel_control_user_r(i),
perf_pmasys_channel_control_membuf_clear_status_doit_f()); perf_pmasys_channel_control_user_membuf_clear_status_doit_f());
} }
for (i = 0U; i < perf_pmasys_channel_mem_bytes__size_1_v(); i++) { for (i = 0U; i < perf_pmasys_channel_mem_bytes__size_1_v(); i++) {

18
drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_perf_ga100.h
View File

@@ -68,11 +68,19 @@
#define perf_pmmfbp_base_v() (0x00200000U) #define perf_pmmfbp_base_v() (0x00200000U)
#define perf_pmmfbp_extent_v() (0x00203fffU) #define perf_pmmfbp_extent_v() (0x00203fffU)
#define perf_pmasys_control_r() (0x0024a000U) #define perf_pmasys_control_r() (0x0024a000U)
#define perf_pmasys_channel_control_r(i)\ #define perf_pmasys_channel_control_user_r(i)\
(nvgpu_safe_add_u32(0x0024a730U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0024a620U, nvgpu_safe_mult_u32((i), 384U)))
#define perf_pmasys_channel_control__size_1_v() (0x00000001U) #define perf_pmasys_channel_control_user__size_1_v() (0x00000001U)
#define perf_pmasys_channel_control_membuf_status_overflowed_f() (0x10U) #define perf_pmasys_channel_control_user_stream_m() (U32(0x1U) << 0U)
#define perf_pmasys_channel_control_membuf_clear_status_doit_f() (0x20U) #define perf_pmasys_channel_control_user_stream_enable_f() (0x1U)
#define perf_pmasys_channel_control_user_stream_disable_f() (0x0U)
#define perf_pmasys_channel_control_user_update_bytes_m() (U32(0x1U) << 31U)
#define perf_pmasys_channel_control_user_update_bytes_doit_f() (0x80000000U)
#define perf_pmasys_channel_control_user_membuf_clear_status_doit_f() (0x2U)
#define perf_pmasys_channel_status_secure_r(i)\
(nvgpu_safe_add_u32(0x0024a610U, nvgpu_safe_mult_u32((i), 384U)))
#define perf_pmasys_channel_status_secure__size_1_v() (0x00000001U)
#define perf_pmasys_channel_status_secure_membuf_status_overflowed_f() (0x1U)
#define perf_pmasys_channel_mem_block_r(i)\ #define perf_pmasys_channel_mem_block_r(i)\
(nvgpu_safe_add_u32(0x0024a638U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0024a638U, nvgpu_safe_mult_u32((i), 4U)))
#define perf_pmasys_channel_mem_block__size_1_v() (0x00000001U) #define perf_pmasys_channel_mem_block__size_1_v() (0x00000001U)

10
drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_perf_ga10b.h
View File

@@ -68,11 +68,6 @@
#define perf_pmmfbp_base_v() (0x00200000U) #define perf_pmmfbp_base_v() (0x00200000U)
#define perf_pmmfbp_extent_v() (0x00203fffU) #define perf_pmmfbp_extent_v() (0x00203fffU)
#define perf_pmasys_control_r() (0x0024a000U) #define perf_pmasys_control_r() (0x0024a000U)
#define perf_pmasys_channel_control_r(i)\
(nvgpu_safe_add_u32(0x0024a730U, nvgpu_safe_mult_u32((i), 4U)))
#define perf_pmasys_channel_control__size_1_v() (0x00000001U)
#define perf_pmasys_channel_control_membuf_status_overflowed_f() (0x10U)
#define perf_pmasys_channel_control_membuf_clear_status_doit_f() (0x20U)
#define perf_pmasys_channel_control_user_r(i)\ #define perf_pmasys_channel_control_user_r(i)\
(nvgpu_safe_add_u32(0x0024a620U, nvgpu_safe_mult_u32((i), 384U))) (nvgpu_safe_add_u32(0x0024a620U, nvgpu_safe_mult_u32((i), 384U)))
#define perf_pmasys_channel_control_user__size_1_v() (0x00000001U) #define perf_pmasys_channel_control_user__size_1_v() (0x00000001U)
@@ -81,6 +76,11 @@
#define perf_pmasys_channel_control_user_stream_disable_f() (0x0U) #define perf_pmasys_channel_control_user_stream_disable_f() (0x0U)
#define perf_pmasys_channel_control_user_update_bytes_m() (U32(0x1U) << 31U) #define perf_pmasys_channel_control_user_update_bytes_m() (U32(0x1U) << 31U)
#define perf_pmasys_channel_control_user_update_bytes_doit_f() (0x80000000U) #define perf_pmasys_channel_control_user_update_bytes_doit_f() (0x80000000U)
#define perf_pmasys_channel_control_user_membuf_clear_status_doit_f() (0x2U)
#define perf_pmasys_channel_status_secure_r(i)\
(nvgpu_safe_add_u32(0x0024a610U, nvgpu_safe_mult_u32((i), 384U)))
#define perf_pmasys_channel_status_secure__size_1_v() (0x00000001U)
#define perf_pmasys_channel_status_secure_membuf_status_overflowed_f() (0x1U)
#define perf_pmasys_channel_mem_block_r(i)\ #define perf_pmasys_channel_mem_block_r(i)\
(nvgpu_safe_add_u32(0x0024a638U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0024a638U, nvgpu_safe_mult_u32((i), 4U)))
#define perf_pmasys_channel_mem_block__size_1_v() (0x00000001U) #define perf_pmasys_channel_mem_block__size_1_v() (0x00000001U)