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Starting from Ampere+ chips, PMASYS control register layout has been re-organized to support multiple PMA streaming channels. In accordance with this update perf HALs to replace legacy register with new registers. The mapping between the legacy register and new register fields can be found here: http://nvbugs/2332044/16. Jira NVGPU-6906 Bug 200737354 Change-Id: I4ed5af7be04f7e2b97a8bf500de3a04cf1e4834c Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2559392 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit