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gpu: nvgpu: Remove early exit from mmu fault

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Disabling / enabling of PFIFO must stay inside the isr.  It cannot be held
disabled outside the isr -- this causes any kind of preemption mechanism to
fail in the presence of an MMU fault until the channel resets the engine.

Bug 1791696

Change-Id: I16600a8571f6555262a75deb305c1d67eb29581a
Signed-off-by: Cory Perry <cperry@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1191026
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Cory Perry
2016-07-26 11:57:24 -07:00
committed by Terje Bergstrom
parent 38a59acc77
commit 1933eb7d18
1 changed files with 3 additions and 9 deletions
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12
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -1407,6 +1407,9 @@ static bool gk20a_fifo_handle_mmu_fault(
/* handled during channel free */
g->fifo.deferred_reset_pending = true;
gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg,
"sm debugger attached,"
" deferring channel recovery to channel free");
} else if (engine_id != ~0) {
was_reset = mutex_is_locked(&g->fifo.gr_reset_mutex);
mutex_lock(&g->fifo.gr_reset_mutex);
@@ -1456,14 +1459,6 @@ static bool gk20a_fifo_handle_mmu_fault(
gk20a_err(dev_from_gk20a(g), "couldn't locate channel for mmu fault");
}
if (g->fifo.deferred_reset_pending) {
gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "sm debugger attached,"
" deferring channel recovery to channel free");
/* clear interrupt */
gk20a_writel(g, fifo_intr_mmu_fault_id_r(), fault_id);
goto exit_enable;
}
/* clear interrupt */
gk20a_writel(g, fifo_intr_mmu_fault_id_r(), fault_id);
@@ -1476,7 +1471,6 @@ static bool gk20a_fifo_handle_mmu_fault(
gr_gpfifo_ctl_access_enabled_f() |
gr_gpfifo_ctl_semaphore_access_enabled_f());
exit_enable:
/* It is safe to enable ELPG again. */
if (support_gk20a_pmu(g->dev) && g->elpg_enabled)
gk20a_pmu_enable_elpg(g);