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gpu: nvgpu: handle pbus and priv intr first

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Handle pbus and priv intr before handling other stall
interrupts. These should be treated as high priority
interrupts.

JIRA NVGPU-25
Bug 200603566

Change-Id: I707119c8751a5621958777ffb64300db28426dfb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2350773
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2020-05-26 15:26:43 -07:00
committed by Alex Waterman
parent ce4e7a6859
commit 1c40ebe9b1
1 changed files with 12 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
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@@ -80,14 +80,21 @@ static u32 mc_gp10b_intr_pending_f(struct gk20a *g, u32 unit)
return intr_pending_f;
}
static void mc_gp10b_isr_stall_primary(struct gk20a *g, u32 mc_intr_0)
{
if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
g->ops.bus.isr(g);
}
if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
g->ops.priv_ring.isr(g);
}
}
static void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0)
{
if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) {
g->ops.mc.ltc_isr(g);
}
if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
g->ops.bus.isr(g);
}
#ifdef CONFIG_NVGPU_DGPU
if ((g->ops.mc.is_intr_nvlink_pending != NULL) &&
g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) {
@@ -112,9 +119,6 @@ static void mc_gp10b_isr_stall_secondary_0(struct gk20a *g, u32 mc_intr_0)
if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) {
g->ops.pmu.pmu_isr(g);
}
if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
g->ops.priv_ring.isr(g);
}
}
static void mc_gp10b_isr_stall_engine(struct gk20a *g,
@@ -186,6 +190,8 @@ void mc_gp10b_isr_stall(struct gk20a *g)
nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x", mc_intr_0);
mc_gp10b_isr_stall_primary(g, mc_intr_0);
for (i = 0U; i < g->fifo.num_engines; i++) {
engine_id = g->fifo.active_engines_list[i];