gpu: nvgpu: falcon2 core loading support

- Added ops for new core.
- Added firmware structs for new core.

JIRA NVGPU-5736

Change-Id: Ifebc8987bf3a749803c1c5539e7d08716c1842a4
Signed-off-by: deepak goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2372104
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/acr/acr.c

@@ -142,11 +142,13 @@ int nvgpu_acr_init(struct gk20a *g)
 		break;
 #endif
 	case NVGPU_GPUID_GV11B:
-#if defined(CONFIG_NVGPU_NEXT)
-	case NVGPU_NEXT_GPUID:
-#endif
 		nvgpu_gv11b_acr_sw_init(g, g->acr);
 		break;
+#if defined(CONFIG_NVGPU_NEXT)
+	case NVGPU_NEXT_GPUID:
+		nvgpu_next_acr_sw_init(g, g->acr);
+		break;
+#endif
 #ifdef CONFIG_NVGPU_DGPU
 	case NVGPU_GPUID_TU104:
 #if defined(CONFIG_NVGPU_NEXT)

drivers/gpu/nvgpu/common/acr/acr_bootstrap.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -24,6 +24,9 @@
 #define ACR_BOOTSTRAP_H
 
 #include "nvgpu_acr_interface.h"
+#ifdef CONFIG_NVGPU_NEXT
+#include "common/acr/nvgpu_next_acr_bootstrap.h"
+#endif
 
 struct gk20a;
 struct nvgpu_acr;
@@ -99,6 +102,12 @@ struct hs_acr {
 
 	/* ACR ucode */
 	const char *acr_fw_name;
+	const char *acr_code_name;
+	const char *acr_data_name;
+	const char *acr_manifest_name;
+	struct nvgpu_firmware *code_fw;
+	struct nvgpu_firmware *data_fw;
+	struct nvgpu_firmware *manifest_fw;
 	struct nvgpu_firmware *acr_fw;
 
 	union{

drivers/gpu/nvgpu/common/acr/acr_priv.h

@@ -140,6 +140,10 @@ struct nvgpu_acr {
 	struct hs_acr acr_ahesasc;
 	struct hs_acr acr_asb;
 
+	/* ACR load split feature support for iGPU*/
+	struct hs_acr acr_alsb;
+	struct hs_acr acr_asc;
+
 	int (*prepare_ucode_blob)(struct gk20a *g);
 	int (*alloc_blob_space)(struct gk20a *g, size_t size,
 		struct nvgpu_mem *mem);

drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c

@@ -154,7 +154,7 @@ static u32 gv11b_acr_lsf_gpccs(struct gk20a *g,
 	return BIT32(lsf->falcon_id);
 }
 
-static u32 gv11b_acr_lsf_conifg(struct gk20a *g,
+u32 gv11b_acr_lsf_config(struct gk20a *g,
 	struct nvgpu_acr *acr)
 {
 	u32 lsf_enable_mask = 0;
@@ -195,7 +195,7 @@ void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
 
 	acr->bootstrap_owner = FALCON_ID_PMU;
 
-	acr->lsf_enable_mask = gv11b_acr_lsf_conifg(g, acr);
+	acr->lsf_enable_mask = gv11b_acr_lsf_config(g, acr);
 
 	gv11b_acr_default_sw_init(g, &acr->acr);
 

drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -28,6 +28,7 @@ struct nvgpu_acr;
 struct hs_acr;
 
 void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
+u32 gv11b_acr_lsf_config(struct gk20a *g, struct nvgpu_acr *acr);
 
 #endif /* ACR_SW_GV11B_H */
 

drivers/gpu/nvgpu/common/falcon/falcon.c

@@ -438,7 +438,7 @@ static int falcon_sw_chip_init(struct gk20a *g, struct nvgpu_falcon *flcn)
 		break;
 #if defined(CONFIG_NVGPU_NEXT)
 	case NVGPU_NEXT_GPUID:
-		gk20a_falcon_sw_init(flcn);
+		nvgpu_next_falcon_sw_init(flcn);
 		break;
 #endif
 #endif

drivers/gpu/nvgpu/include/nvgpu/falcon.h

@@ -215,6 +215,8 @@ struct nvgpu_falcon {
 	u32 flcn_id;
 	/** Base address to access falcon registers */
 	u32 flcn_base;
+	/** Base address to access nextcore registers */
+	u32 flcn2_base;
 	/** Indicates if the falcon is supported and initialized for use. */
 	bool is_falcon_supported;
 	/** Indicates if the falcon interrupts are enabled. */

drivers/gpu/nvgpu/include/nvgpu/gops/falcon.h

@@ -50,7 +50,11 @@ struct gops_falcon {
 	int (*copy_to_imem)(struct nvgpu_falcon *flcn,
 			    u32 dst, u8 *src, u32 size, u8 port,
 			    bool sec, u32 tag);
+	void (*set_bcr)(struct nvgpu_falcon *flcn);
+	void (*dump_brom_stats)(struct nvgpu_falcon *flcn);
+	u32  (*get_brom_retcode)(struct nvgpu_falcon *flcn);
 	u32 (*dmemc_blk_mask)(void);
+	bool (*check_brom_passed)(u32 retcode);
 	u32 (*imemc_blk_field)(u32 blk);
 	void (*bootstrap)(struct nvgpu_falcon *flcn,
 			 u32 boot_vector);

drivers/gpu/nvgpu/include/nvgpu/gops/gsp.h

@@ -28,6 +28,7 @@ struct gk20a;
 
 struct gops_gsp {
 	u32 (*falcon_base_addr)(void);
+	u32 (*falcon2_base_addr)(void);
 	void (*falcon_setup_boot_config)(struct gk20a *g);
 	int (*gsp_reset)(struct gk20a *g);
 };

drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h

@@ -209,6 +209,16 @@ struct gops_pmu {
 	 */
 	u32 (*falcon_base_addr)(void);
 
+	/**
+	 * @brief Fetch base address of PMU Engine Falcon2.
+	 *
+	 * @param void
+	 *
+	 * @return Chip specific PMU Engine Falcon2 base address.
+	 *         For NEXT_GPUID, NEXT_GPUID PMU Engine Falcon2 base address
+	 *         will be returned.
+	 */
+	u32 (*falcon2_base_addr)(void);
 	/**
 	 * @brief Checks if PMU DEBUG fuse is blown or not
 	 *