nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Add physical gpu instance support

Browse Source 
This patch added the physical gpu intance support when MIG
is enabled.

JIRA NVGPU-5647

Change-Id: Ic642b88ebc70ea6114e63c2287db8bca00860c67
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2410698
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Lakshmanan M
2020-09-09 11:02:40 +05:30
committed by Alex Waterman
parent 5d740f98b0
commit 47dc015b86
3 changed files with 59 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

64
drivers/gpu/nvgpu/common/grmgr/grmgr.c
View File

@@ -43,6 +43,7 @@ int nvgpu_init_gr_manager(struct gk20a *g)
gpu_instance->gpu_instance_id = 0U;
gpu_instance->is_memory_partition_supported = false;
gpu_instance->gpu_instance_type = NVGPU_MIG_TYPE_PHYSICAL;
gr_syspipe->gr_instance_id = 0U;
gr_syspipe->gr_syspipe_id = 0U;
@@ -79,7 +80,7 @@ int nvgpu_init_gr_manager(struct gk20a *g)
g->mig.current_gr_syspipe_id = NVGPU_MIG_INVALID_GR_SYSPIPE_ID;
nvgpu_log(g, gpu_dbg_mig,
"[non MIG boot] gpu_instance_id[%u] gr_instance_id[%u] "
"[Physical device] gpu_instance_id[%u] gr_instance_id[%u] "
"gr_syspipe_id[%u] num_gpc[%u] gr_engine_id[%u] "
"max_veid_count_per_tsg[%u] veid_start_offset[%u] "
"is_memory_partition_support[%d] num_lce[%u] ",
@@ -250,47 +251,66 @@ u32 nvgpu_grmgr_get_num_gr_instances(struct gk20a *g)
return g->mig.num_gr_sys_pipes_enabled;
}
static inline u32 nvgpu_grmgr_get_gpu_instance_id(struct gk20a *g,
u32 gr_instance_id)
{
u32 gpu_instance_id = 0U;
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
/* 0th entry is physical device gpu instance */
gpu_instance_id = nvgpu_safe_add_u32(gr_instance_id, 1U);
if (gpu_instance_id >= g->mig.num_gpu_instances) {
nvgpu_err(g,
"gpu_instance_id[%u] > num_gpu_instances[%u]",
gpu_instance_id, g->mig.num_gpu_instances);
nvgpu_assert(
gpu_instance_id < g->mig.num_gpu_instances);
gpu_instance_id = 0U;
}
}
nvgpu_log(g, gpu_dbg_mig, "gr_instance_id[%u] gpu_instance_id[%u]",
gr_instance_id, gpu_instance_id);
return gpu_instance_id;
}
u32 nvgpu_grmgr_get_gr_syspipe_id(struct gk20a *g, u32 gr_instance_id)
{
struct nvgpu_gpu_instance *gpu_instance;
struct nvgpu_gr_syspipe *gr_syspipe;
u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id(
g, gr_instance_id);
if (gr_instance_id < g->mig.num_gpu_instances) {
gpu_instance = &g->mig.gpu_instance[gr_instance_id];
gr_syspipe = &gpu_instance->gr_syspipe;
gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
gr_syspipe = &gpu_instance->gr_syspipe;
return gr_syspipe->gr_syspipe_id;
}
return U32_MAX;
return gr_syspipe->gr_syspipe_id;
}
u32 nvgpu_grmgr_get_gr_num_gpcs(struct gk20a *g, u32 gr_instance_id)
{
struct nvgpu_gpu_instance *gpu_instance;
struct nvgpu_gr_syspipe *gr_syspipe;
u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id(
g, gr_instance_id);
if (gr_instance_id < g->mig.num_gpu_instances) {
gpu_instance = &g->mig.gpu_instance[gr_instance_id];
gr_syspipe = &gpu_instance->gr_syspipe;
gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
gr_syspipe = &gpu_instance->gr_syspipe;
return gr_syspipe->num_gpc;
}
return U32_MAX;
return gr_syspipe->num_gpc;
}
u32 nvgpu_grmgr_get_gr_gpc_phys_id(struct gk20a *g, u32 gr_instance_id, u32 gpc_local_id)
{
struct nvgpu_gpu_instance *gpu_instance;
struct nvgpu_gr_syspipe *gr_syspipe;
u32 gpu_instance_id = nvgpu_grmgr_get_gpu_instance_id(
g, gr_instance_id);
if (gr_instance_id < g->mig.num_gpu_instances) {
gpu_instance = &g->mig.gpu_instance[gr_instance_id];
gr_syspipe = &gpu_instance->gr_syspipe;
gpu_instance = &g->mig.gpu_instance[gpu_instance_id];
gr_syspipe = &gpu_instance->gr_syspipe;
return gr_syspipe->gpcs[gpc_local_id].physical_id;
}
return U32_MAX;
return gr_syspipe->gpcs[gpc_local_id].physical_id;
}

7
drivers/gpu/nvgpu/include/nvgpu/grmgr.h
View File

@@ -26,6 +26,7 @@
#define NVGPU_GRMGR_H
#include <nvgpu/types.h>
#include <nvgpu/mig.h>
struct gk20a;
@@ -38,4 +39,10 @@ u32 nvgpu_grmgr_get_gr_syspipe_id(struct gk20a *g, u32 gr_instance_id);
u32 nvgpu_grmgr_get_gr_num_gpcs(struct gk20a *g, u32 gr_instance_id);
u32 nvgpu_grmgr_get_gr_gpc_phys_id(struct gk20a *g, u32 gr_instance_id, u32 gpc_local_id);
static inline bool nvgpu_grmgr_is_mig_type_gpu_instance(
struct nvgpu_gpu_instance *gpu_instance)
{
return (gpu_instance->gpu_instance_type == NVGPU_MIG_TYPE_MIG);
}
#endif /* NVGPU_GRMGR_H */

12
drivers/gpu/nvgpu/include/nvgpu/mig.h
View File

@@ -29,8 +29,8 @@
/** Maximum GPC group supported by HW. */
#define NVGPU_MIG_MAX_GPCGRP 2U
/** Maximum gpu instances count. */
#define NVGPU_MIG_MAX_GPU_INSTANCES 8U
/** Maximum gpu instances count (1 Physical + 8 MIGs). */
#define NVGPU_MIG_MAX_GPU_INSTANCES 9U
/** Maximum mig config count. */
#define NVGPU_MIG_MAX_MIG_CONFIG_COUNT 16U
@@ -47,6 +47,12 @@
/** Maximum number of GPC count. */
#define NVGPU_MIG_MAX_GPCS 32U
/** Enumerated type used to identify various gpu instance types */
enum nvgpu_mig_gpu_instance_type {
NVGPU_MIG_TYPE_PHYSICAL = 0,
NVGPU_MIG_TYPE_MIG
};
/**
* @brief GPC Id information.
* This struct describes the logical, physical and gpcgrp id of each GPC.
@@ -108,6 +114,8 @@ struct nvgpu_gpu_instance {
const struct nvgpu_device *lce_devs[NVGPU_MIG_MAX_ENGINES];
/* Flag to indicate whether memory partition is supported or not. */
bool is_memory_partition_supported;
/** Enumerated type used to identify various gpu instance types */
enum nvgpu_mig_gpu_instance_type gpu_instance_type;
};
/**