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gpu: nvgpu: fix misra 2.5 violations

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MISRA Advisory Rule 2.5 states that a project should not contain unused
macro declarations.

While most of the violations in the nvgpu driver are due to unused
macros from hw headers, devinit-related headers, etc. there is a small
number that are due to things like:

 * macros not being used when they could/should be
 * macros in C files that are really not referenced
 * CPP build flag mismatches

This change eliminates such violations from the following:

 * replace constants with existing macros in timeout conversion code
 * wrap nvgpu_gmmu_dbg macro #defines in #ifdef CONFIG_NVGPU_TRACE/#endif
 * wrap MAX_MC_INTR_REGS #define in #ifdef CONFIG_NVGPU_NON_FUSA/#endif
 * remove unused FECS_MAILBOX_0_ACK_RESTORE from runlist code
 * wrap BACKTRACE_MAXSIZE macro with #ifndef _QNX_SOURCE/#endif

Jira NVGPU-3178

Change-Id: I2bc72f706d7af3f8e7b062126e8543d0dc8ac250
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284419
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Scott Long
2020-01-23 11:09:36 -08:00
committed by Alex Waterman
parent 11b34e891f
commit 21f8b366cd
5 changed files with 16 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/common/mm/gmmu/page_table.c
View File

@@ -37,7 +37,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/static_analysis.h>
#ifdef CONFIG_NVGPU_TRACE
#define nvgpu_gmmu_dbg(g, attrs, fmt, args...) \
do { \
if ((attrs)->debug) { \
@@ -57,6 +57,7 @@ NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \
} \
NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_4), "Bug 2623654") \
} while (false)
#endif
static int pd_allocate(struct vm_gk20a *vm,
struct nvgpu_gmmu_pd *pd,

4
drivers/gpu/nvgpu/hal/fifo/runlist_fifo_gk20a_fusa.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -33,8 +33,6 @@
#include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
#define FECS_MAILBOX_0_ACK_RESTORE 0x4U
u32 gk20a_runlist_length_max(struct gk20a *g)
{
return fifo_eng_runlist_length_max_v();

2
drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
View File

@@ -25,7 +25,9 @@
#include <nvgpu/types.h>
#ifdef CONFIG_NVGPU_NON_FUSA
#define MAX_MC_INTR_REGS 2U
#endif
struct gk20a;
enum nvgpu_unit;

2
drivers/gpu/nvgpu/os/posix/bug.c
View File

@@ -35,7 +35,9 @@
#include <signal.h>
#endif
#ifndef _QNX_SOURCE
#define BACKTRACE_MAXSIZE 1024
#endif
struct nvgpu_bug_desc {
bool in_use;

18
drivers/gpu/nvgpu/os/posix/timers.c
View File

@@ -28,7 +28,6 @@
#include <nvgpu/timers.h>
#include <nvgpu/soc.h>
#define MSEC_PER_SEC 1000
#define USEC_PER_MSEC 1000
#define NSEC_PER_USEC 1000
#define NSEC_PER_MSEC 1000000
@@ -74,7 +73,7 @@ s64 nvgpu_current_time_us(void)
BUG();
}
time_now = nvgpu_safe_mult_s64((s64)now.tv_sec, (s64)1000000);
time_now = nvgpu_safe_mult_s64((s64)now.tv_sec, (s64)NSEC_PER_MSEC);
time_now = nvgpu_safe_add_s64(time_now, (s64)now.tv_usec);
return time_now;
@@ -87,7 +86,7 @@ static s64 get_time_ns(void)
(void) clock_gettime(CLOCK_MONOTONIC, &ts);
t_ns = nvgpu_safe_mult_s64(ts.tv_sec, 1000000000);
t_ns = nvgpu_safe_mult_s64(ts.tv_sec, NSEC_PER_SEC);
t_ns = nvgpu_safe_add_s64(t_ns, ts.tv_nsec);
return t_ns;
@@ -151,11 +150,11 @@ static void nvgpu_usleep(unsigned int usecs)
t_currentns = get_time_ns();
t_ns = (s64)usecs;
t_ns = nvgpu_safe_mult_s64(t_ns, 1000);
t_ns = nvgpu_safe_mult_s64(t_ns, NSEC_PER_USEC);
t_ns = nvgpu_safe_add_s64(t_ns, t_currentns);
rqtp.tv_sec = t_ns / 1000000000;
rqtp.tv_nsec = t_ns % 1000000000;
rqtp.tv_sec = t_ns / NSEC_PER_SEC;
rqtp.tv_nsec = t_ns % NSEC_PER_SEC;
(void) clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &rqtp, NULL);
}
@@ -181,11 +180,12 @@ void nvgpu_msleep(unsigned int msecs)
t_currentns = get_time_ns();
t_ns = (s64)msecs;
t_ns = nvgpu_safe_mult_s64(t_ns, 1000000);
t_ns = nvgpu_safe_mult_s64(t_ns, NSEC_PER_MSEC);
t_ns = nvgpu_safe_add_s64(t_ns, t_currentns);
rqtp.tv_sec = t_ns / 1000000000;
rqtp.tv_nsec = t_ns % 1000000000;
rqtp.tv_sec = t_ns / NSEC_PER_SEC;
rqtp.tv_nsec = t_ns % NSEC_PER_SEC;
(void) clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &rqtp, NULL);
}