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gpu: nvgpu: rearrange pmu_save hal function

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As part of creating zbc as gr subunit, move pmu_save hal function
from zbc to pmu hal.
This hal function is used to pass the information to gpmu
firmware, which should reside as part of pmu.

remove pmu_save hal from zbc.
add save_zbc hal under pmu.
remove unused function gr_gk20a_pmu_save_zbc

JIRA NVGPU-1882

Change-Id: I132dbc7a9ee9755043cd08f288344df447e28af6
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018581
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-02-13 12:35:07 -08:00
committed by mobile promotions
parent a9c2a2defd
commit 220ba0dfa4
11 changed files with 10 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/pmu/pmu.c
View File

@@ -577,7 +577,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g)
if (nvgpu_is_enabled(g, NVGPU_PMU_ZBC_SAVE)) {
/* Save zbc table after PMU is initialized. */
pmu->zbc_ready = true;
g->ops.gr.zbc.pmu_save(g, 0xf);
g->ops.pmu.save_zbc(g, 0xf);
}
if (g->elpg_enabled) {

2
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -308,7 +308,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.add_depth = NULL,
.set_table = vgpu_gr_add_zbc,
.query_table = vgpu_gr_query_zbc,
.pmu_save = NULL,
.stencil_query_table = NULL,
.load_stencil_default_tbl = NULL,
.add_type_stencil = NULL,
@@ -551,6 +550,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.dump_secure_fuses = NULL,
.reset_engine = NULL,
.is_engine_in_reset = NULL,
.save_zbc = NULL,
},
.clk_arb = {
.check_clk_arb_support = gp10b_check_clk_arb_support,

2
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -348,7 +348,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.add_depth = NULL,
.set_table = vgpu_gr_add_zbc,
.query_table = vgpu_gr_query_zbc,
.pmu_save = NULL,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
@@ -625,6 +624,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.pmu_nsbootstrap = NULL,
.pmu_pg_set_sub_feature_mask = NULL,
.is_pmu_supported = NULL,
.save_zbc = NULL,
},
.clk_arb = {
.check_clk_arb_support = gp10b_check_clk_arb_support,

37
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -2562,41 +2562,6 @@ int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
return 0;
}
void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries)
{
struct fifo_gk20a *f = &g->fifo;
struct fifo_engine_info_gk20a *gr_info = NULL;
int ret;
u32 engine_id;
engine_id = nvgpu_engine_get_gr_eng_id(g);
gr_info = (f->engine_info + engine_id);
ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
if (ret != 0) {
nvgpu_err(g,
"failed to disable gr engine activity");
return;
}
ret = g->ops.gr.wait_empty(g);
if (ret != 0) {
nvgpu_err(g,
"failed to idle graphics");
goto clean_up;
}
/* update zbc */
g->ops.gr.zbc.pmu_save(g, entries);
clean_up:
ret = gk20a_fifo_enable_engine_activity(g, gr_info);
if (ret != 0) {
nvgpu_err(g,
"failed to enable gr engine activity");
}
}
int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *zbc_val)
{
@@ -2702,7 +2667,7 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
/* update zbc for elpg only when new entry is added */
entries = max(gr->max_used_color_index,
gr->max_used_depth_index);
g->ops.gr.zbc.pmu_save(g, entries);
g->ops.pmu.save_zbc(g, entries);
}
err_mutex:

1
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -548,7 +548,6 @@ int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *color_val, u32 index);
int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *depth_val, u32 index);
void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries);
int gr_gk20a_wait_idle(struct gk20a *g);
int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
bool *post_event, struct channel_gk20a *fault_ch,

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -415,7 +415,6 @@ static const struct gpu_ops gm20b_ops = {
.add_depth = gr_gk20a_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.pmu_save = gk20a_pmu_save_zbc,
.stencil_query_table = NULL,
.load_stencil_default_tbl = NULL,
.add_type_stencil = NULL,
@@ -674,6 +673,7 @@ static const struct gpu_ops gm20b_ops = {
.is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
.get_irqdest = gk20a_pmu_get_irqdest,
.is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en,
.save_zbc = gk20a_pmu_save_zbc,
},
.clk = {
.init_clk_support = gm20b_init_clk_support,

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -458,7 +458,6 @@ static const struct gpu_ops gp10b_ops = {
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.pmu_save = gk20a_pmu_save_zbc,
.stencil_query_table = NULL,
.load_stencil_default_tbl = NULL,
.add_type_stencil = NULL,
@@ -745,6 +744,7 @@ static const struct gpu_ops gp10b_ops = {
.is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
.get_irqdest = gk20a_pmu_get_irqdest,
.is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en,
.save_zbc = gk20a_pmu_save_zbc,
},
.clk_arb = {
.check_clk_arb_support = gp10b_check_clk_arb_support,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -584,7 +584,6 @@ static const struct gpu_ops gv100_ops = {
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.pmu_save = gk20a_pmu_save_zbc,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
@@ -927,6 +926,7 @@ static const struct gpu_ops gv100_ops = {
.setup_apertures = gp106_pmu_setup_apertures,
.secured_pmu_start = gm20b_secured_pmu_start,
.create_ssmd_lookup_table = nvgpu_pmu_create_ssmd_lookup_table,
.save_zbc = gk20a_pmu_save_zbc,
},
.clk = {
.init_clk_support = gv100_init_clk_support,

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -543,7 +543,6 @@ static const struct gpu_ops gv11b_ops = {
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.pmu_save = gk20a_pmu_save_zbc,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
@@ -873,6 +872,7 @@ static const struct gpu_ops gv11b_ops = {
.get_irqdest = gv11b_pmu_get_irqdest,
.handle_ext_irq = gv11b_pmu_handle_ext_irq,
.is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en,
.save_zbc = gk20a_pmu_save_zbc,
},
.clk_arb = {
.check_clk_arb_support = gp10b_check_clk_arb_support,

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -629,7 +629,6 @@ struct gpu_ops {
struct gr_gk20a *gr);
int (*add_stencil)(struct gk20a *g, struct gr_gk20a *gr,
struct zbc_entry *s_val, u32 index);
void (*pmu_save)(struct gk20a *g, u32 entries);
bool (*add_type_stencil)(struct gk20a *g,
struct gr_gk20a *gr,
struct zbc_entry *zbc_val, int *ret_val);
@@ -1253,6 +1252,7 @@ struct gpu_ops {
u64 err_cnt);
} err_ops;
void (*create_ssmd_lookup_table)(struct nvgpu_pmu *pmu);
void (*save_zbc)(struct gk20a *g, u32 entries);
} pmu;
struct {
int (*init_debugfs)(struct gk20a *g);

2
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -608,7 +608,6 @@ static const struct gpu_ops tu104_ops = {
.add_depth = gr_gp10b_add_zbc_depth,
.set_table = gk20a_gr_zbc_set_table,
.query_table = gr_gk20a_query_zbc,
.pmu_save = gk20a_pmu_save_zbc,
.stencil_query_table = gr_gv11b_zbc_s_query_table,
.load_stencil_default_tbl =
gr_gv11b_load_stencil_default_tbl,
@@ -959,6 +958,7 @@ static const struct gpu_ops tu104_ops = {
.setup_apertures = gp106_pmu_setup_apertures,
.secured_pmu_start = gm20b_secured_pmu_start,
.create_ssmd_lookup_table = nvgpu_pmu_create_ssmd_lookup_table,
.save_zbc = gk20a_pmu_save_zbc,
},
.clk = {
.init_clk_support = gv100_init_clk_support,