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gpu: nvgpu: ga10b: add fuse_ctrl register

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Add the following registers:
fuse_ctrl_opt_gpc_r()
fuse_ctrl_opt_fbp_r()

These registers are needed to add floorsweeping support
for GPC and FBP

JIRA NVGPU-6433

Change-Id: I795e0812bd9abb69cdf552b8ccb460f026a06803
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2559485
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Divya Singhatwaria
2021-03-23 18:34:12 +05:30
committed by mobile promotions
parent 860027dc8c
commit 22c3ce37a7
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_fuse_ga10b.h
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@@ -66,6 +66,8 @@
(nvgpu_safe_add_u32(0x00820838U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_ltc_fbp_r(i)\
(nvgpu_safe_add_u32(0x00820970U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_gpc_r() (0x0082081cU)
#define fuse_ctrl_opt_fbp_r() (0x00820938U)
#define fuse_status_opt_fbio_r() (0x00820c14U)
#define fuse_status_opt_fbp_r() (0x00820d38U)
#define fuse_opt_ecc_en_r() (0x00820228U)