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gpu: nvgpu: move fbp_en_mask hal to hal.gr.init

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Move fbp_en_mask hal to hal.gr.init.

Calls to g->ops.gr.fbp_en_mask is modified to
g->ops.gr.init.fbp_en_mask

JIRA NVGPU-2951

Change-Id: I555ec3691226a9dd8555fa91f5ec90010d83ddd3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081370
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-03-25 18:08:50 -07:00
committed by mobile promotions
parent 2e68f784b0
commit 22cb47c077
14 changed files with 33 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
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@@ -143,7 +143,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
gr_gp10b_update_ctxsw_preemption_mode, gr_gp10b_update_ctxsw_preemption_mode,
.dump_gr_regs = NULL, .dump_gr_regs = NULL,
.update_pc_sampling = vgpu_gr_update_pc_sampling, .update_pc_sampling = vgpu_gr_update_pc_sampling,
.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
.get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
.init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
.init_cyclestats = vgpu_gr_init_cyclestats, .init_cyclestats = vgpu_gr_init_cyclestats,
@@ -318,6 +317,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
}, },
#endif /* CONFIG_GK20A_CTXSW_TRACE */ #endif /* CONFIG_GK20A_CTXSW_TRACE */
.init = { .init = {
.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
.fs_state = vgpu_gr_init_fs_state, .fs_state = vgpu_gr_init_fs_state,
.get_bundle_cb_default_size = .get_bundle_cb_default_size =
gm20b_gr_init_get_bundle_cb_default_size, gm20b_gr_init_get_bundle_cb_default_size,

2
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
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@@ -164,7 +164,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
gr_gv11b_update_ctxsw_preemption_mode, gr_gv11b_update_ctxsw_preemption_mode,
.dump_gr_regs = NULL, .dump_gr_regs = NULL,
.update_pc_sampling = vgpu_gr_update_pc_sampling, .update_pc_sampling = vgpu_gr_update_pc_sampling,
.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
.get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
.init_cyclestats = vgpu_gr_init_cyclestats, .init_cyclestats = vgpu_gr_init_cyclestats,
@@ -369,6 +368,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
}, },
#endif /* CONFIG_GK20A_CTXSW_TRACE */ #endif /* CONFIG_GK20A_CTXSW_TRACE */
.init = { .init = {
.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
.fs_state = vgpu_gr_init_fs_state, .fs_state = vgpu_gr_init_fs_state,
.get_bundle_cb_default_size = .get_bundle_cb_default_size =
gv11b_gr_init_get_bundle_cb_default_size, gv11b_gr_init_get_bundle_cb_default_size,

2
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -1770,7 +1770,7 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
gr->num_fbps = g->ops.priv_ring.get_fbp_count(g); gr->num_fbps = g->ops.priv_ring.get_fbp_count(g);
gr->max_fbps_count = g->ops.top.get_max_fbps_count(g); gr->max_fbps_count = g->ops.top.get_max_fbps_count(g);
gr->fbp_en_mask = g->ops.gr.get_fbp_en_mask(g); gr->fbp_en_mask = g->ops.gr.init.get_fbp_en_mask(g);
if (gr->fbp_rop_l2_en_mask == NULL) { if (gr->fbp_rop_l2_en_mask == NULL) {
gr->fbp_rop_l2_en_mask = gr->fbp_rop_l2_en_mask =

22
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
View File

@@ -718,26 +718,6 @@ int gr_gm20b_update_pc_sampling(struct channel_gk20a *c,
return 0; return 0;
} }
u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g)
{
u32 fbp_en_mask;
u32 max_fbps_count;
max_fbps_count = g->ops.top.get_max_fbps_count(g);
/*
* Read active fbp mask from fuse
* Note that 0:enable and 1:disable in value read from fuse so we've to
* flip the bits.
* Also set unused bits to zero
*/
fbp_en_mask = g->ops.fuse.fuse_status_opt_fbp(g);
fbp_en_mask = ~fbp_en_mask;
fbp_en_mask = fbp_en_mask & (BIT32(max_fbps_count) - 1U);
return fbp_en_mask;
}
u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g) u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g)
{ {
struct gr_gk20a *gr = &g->gr; struct gr_gk20a *gr = &g->gr;
@@ -749,7 +729,7 @@ u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g)
max_fbps_count = g->ops.top.get_max_fbps_count(g); max_fbps_count = g->ops.top.get_max_fbps_count(g);
max_ltc_per_fbp = g->ops.top.get_max_ltc_per_fbp(g); max_ltc_per_fbp = g->ops.top.get_max_ltc_per_fbp(g);
rop_l2_all_en = BIT32(max_ltc_per_fbp) - 1U; rop_l2_all_en = BIT32(max_ltc_per_fbp) - 1U;
fbp_en_mask = gr_gm20b_get_fbp_en_mask(g); fbp_en_mask = g->ops.gr.init.get_fbp_en_mask(g);
/* mask of Rop_L2 for each FBP */ /* mask of Rop_L2 for each FBP */
for_each_set_bit(i, &fbp_en_mask, max_fbps_count) { for_each_set_bit(i, &fbp_en_mask, max_fbps_count) {

1
drivers/gpu/nvgpu/gm20b/gr_gm20b.h
View File

@@ -79,7 +79,6 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
struct gk20a_debug_output *o); struct gk20a_debug_output *o);
int gr_gm20b_update_pc_sampling(struct channel_gk20a *c, int gr_gm20b_update_pc_sampling(struct channel_gk20a *c,
bool enable); bool enable);
u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g);
u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g); u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g);
void gr_gm20b_init_cyclestats(struct gk20a *g); void gr_gm20b_init_cyclestats(struct gk20a *g);
void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state);

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
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@@ -268,7 +268,6 @@ static const struct gpu_ops gm20b_ops = {
gr_gm20b_update_ctxsw_preemption_mode, gr_gm20b_update_ctxsw_preemption_mode,
.dump_gr_regs = gr_gm20b_dump_gr_status_regs, .dump_gr_regs = gr_gm20b_dump_gr_status_regs,
.update_pc_sampling = gr_gm20b_update_pc_sampling, .update_pc_sampling = gr_gm20b_update_pc_sampling,
.get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
.get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
.init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
.init_cyclestats = gr_gm20b_init_cyclestats, .init_cyclestats = gr_gm20b_init_cyclestats,
@@ -412,6 +411,7 @@ static const struct gpu_ops gm20b_ops = {
.program_zcull_mapping = gm20b_gr_program_zcull_mapping, .program_zcull_mapping = gm20b_gr_program_zcull_mapping,
}, },
.init = { .init = {
.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,
.lg_coalesce = gm20b_gr_init_lg_coalesce, .lg_coalesce = gm20b_gr_init_lg_coalesce,
.su_coalesce = gm20b_gr_init_su_coalesce, .su_coalesce = gm20b_gr_init_su_coalesce,
.pes_vsc_stream = gm20b_gr_init_pes_vsc_stream, .pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -293,7 +293,6 @@ static const struct gpu_ops gp10b_ops = {
gr_gp10b_update_ctxsw_preemption_mode, gr_gp10b_update_ctxsw_preemption_mode,
.dump_gr_regs = gr_gp10b_dump_gr_status_regs, .dump_gr_regs = gr_gp10b_dump_gr_status_regs,
.update_pc_sampling = gr_gm20b_update_pc_sampling, .update_pc_sampling = gr_gm20b_update_pc_sampling,
.get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
.get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
.init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
.init_cyclestats = gr_gm20b_init_cyclestats, .init_cyclestats = gr_gm20b_init_cyclestats,
@@ -485,6 +484,7 @@ static const struct gpu_ops gp10b_ops = {
.program_zcull_mapping = gm20b_gr_program_zcull_mapping, .program_zcull_mapping = gm20b_gr_program_zcull_mapping,
}, },
.init = { .init = {
.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,
.lg_coalesce = gm20b_gr_init_lg_coalesce, .lg_coalesce = gm20b_gr_init_lg_coalesce,
.su_coalesce = gm20b_gr_init_su_coalesce, .su_coalesce = gm20b_gr_init_su_coalesce,
.pes_vsc_stream = gm20b_gr_init_pes_vsc_stream, .pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -405,7 +405,6 @@ static const struct gpu_ops gv100_ops = {
gr_gp10b_update_ctxsw_preemption_mode, gr_gp10b_update_ctxsw_preemption_mode,
.dump_gr_regs = gr_gv11b_dump_gr_status_regs, .dump_gr_regs = gr_gv11b_dump_gr_status_regs,
.update_pc_sampling = gr_gm20b_update_pc_sampling, .update_pc_sampling = gr_gm20b_update_pc_sampling,
.get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
.get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
.init_cyclestats = gr_gm20b_init_cyclestats, .init_cyclestats = gr_gm20b_init_cyclestats,
@@ -629,6 +628,7 @@ static const struct gpu_ops gv100_ops = {
gv100_gr_hwpm_map_get_active_fbpa_mask, gv100_gr_hwpm_map_get_active_fbpa_mask,
}, },
.init = { .init = {
.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,
.lg_coalesce = gm20b_gr_init_lg_coalesce, .lg_coalesce = gm20b_gr_init_lg_coalesce,
.su_coalesce = gm20b_gr_init_su_coalesce, .su_coalesce = gm20b_gr_init_su_coalesce,
.pes_vsc_stream = gm20b_gr_init_pes_vsc_stream, .pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -357,7 +357,6 @@ static const struct gpu_ops gv11b_ops = {
gr_gv11b_update_ctxsw_preemption_mode, gr_gv11b_update_ctxsw_preemption_mode,
.dump_gr_regs = gr_gv11b_dump_gr_status_regs, .dump_gr_regs = gr_gv11b_dump_gr_status_regs,
.update_pc_sampling = gr_gm20b_update_pc_sampling, .update_pc_sampling = gr_gm20b_update_pc_sampling,
.get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
.get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
.init_cyclestats = gr_gm20b_init_cyclestats, .init_cyclestats = gr_gm20b_init_cyclestats,
@@ -588,6 +587,7 @@ static const struct gpu_ops gv11b_ops = {
gv100_gr_hwpm_map_align_regs_perf_pma, gv100_gr_hwpm_map_align_regs_perf_pma,
}, },
.init = { .init = {
.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,
.lg_coalesce = gm20b_gr_init_lg_coalesce, .lg_coalesce = gm20b_gr_init_lg_coalesce,
.su_coalesce = gm20b_gr_init_su_coalesce, .su_coalesce = gm20b_gr_init_su_coalesce,
.pes_vsc_stream = gm20b_gr_init_pes_vsc_stream, .pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,

21
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
View File

@@ -43,6 +43,26 @@
#define FE_PWR_MODE_TIMEOUT_DEFAULT_US 10U #define FE_PWR_MODE_TIMEOUT_DEFAULT_US 10U
#define FECS_CTXSW_RESET_DELAY_US 10U #define FECS_CTXSW_RESET_DELAY_US 10U
u32 gm20b_gr_init_get_fbp_en_mask(struct gk20a *g)
{
u32 fbp_en_mask;
u32 max_fbps_count;
max_fbps_count = g->ops.top.get_max_fbps_count(g);
/*
* Read active fbp mask from fuse
* Note that 0:enable and 1:disable in value read from fuse so we've to
* flip the bits.
* Also set unused bits to zero
*/
fbp_en_mask = g->ops.fuse.fuse_status_opt_fbp(g);
fbp_en_mask = ~fbp_en_mask;
fbp_en_mask = fbp_en_mask & (BIT32(max_fbps_count) - 1U);
return fbp_en_mask;
}
void gm20b_gr_init_lg_coalesce(struct gk20a *g, u32 data) void gm20b_gr_init_lg_coalesce(struct gk20a *g, u32 data)
{ {
u32 val; u32 val;
@@ -71,6 +91,7 @@ void gm20b_gr_init_su_coalesce(struct gk20a *g, u32 data)
void gm20b_gr_init_pes_vsc_stream(struct gk20a *g) void gm20b_gr_init_pes_vsc_stream(struct gk20a *g)
{ {
u32 data = nvgpu_readl(g, gr_gpc0_ppc0_pes_vsc_strem_r()); u32 data = nvgpu_readl(g, gr_gpc0_ppc0_pes_vsc_strem_r());
data = set_field(data, gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(), data = set_field(data, gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(),
gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f()); gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f());
nvgpu_writel(g, gr_gpc0_ppc0_pes_vsc_strem_r(), data); nvgpu_writel(g, gr_gpc0_ppc0_pes_vsc_strem_r(), data);

1
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h
View File

@@ -31,6 +31,7 @@ struct nvgpu_gr_config;
struct netlist_av_list; struct netlist_av_list;
struct nvgpu_gr_config; struct nvgpu_gr_config;
u32 gm20b_gr_init_get_fbp_en_mask(struct gk20a *g);
void gm20b_gr_init_lg_coalesce(struct gk20a *g, u32 data); void gm20b_gr_init_lg_coalesce(struct gk20a *g, u32 data);
void gm20b_gr_init_su_coalesce(struct gk20a *g, u32 data); void gm20b_gr_init_su_coalesce(struct gk20a *g, u32 data);
void gm20b_gr_init_pes_vsc_stream(struct gk20a *g); void gm20b_gr_init_pes_vsc_stream(struct gk20a *g);

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -335,7 +335,6 @@ struct gpu_ops {
struct gk20a_debug_output *o); struct gk20a_debug_output *o);
int (*update_pc_sampling)(struct channel_gk20a *ch, int (*update_pc_sampling)(struct channel_gk20a *ch,
bool enable); bool enable);
u32 (*get_fbp_en_mask)(struct gk20a *g);
u32* (*get_rop_l2_en_mask)(struct gk20a *g); u32* (*get_rop_l2_en_mask)(struct gk20a *g);
void (*init_sm_dsm_reg_info)(void); void (*init_sm_dsm_reg_info)(void);
void (*init_ovr_sm_dsm_perf)(void); void (*init_ovr_sm_dsm_perf)(void);
@@ -661,6 +660,7 @@ struct gpu_ops {
} hwpm_map; } hwpm_map;
struct { struct {
u32 (*get_fbp_en_mask)(struct gk20a *g);
void (*lg_coalesce)(struct gk20a *g, u32 data); void (*lg_coalesce)(struct gk20a *g, u32 data);
void (*su_coalesce)(struct gk20a *g, u32 data); void (*su_coalesce)(struct gk20a *g, u32 data);
void (*pes_vsc_stream)(struct gk20a *g); void (*pes_vsc_stream)(struct gk20a *g);

2
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -338,7 +338,7 @@ gk20a_ctrl_ioctl_gpu_characteristics(
strlcpy(gpu.chipname, g->name, sizeof(gpu.chipname)); strlcpy(gpu.chipname, g->name, sizeof(gpu.chipname));
gpu.max_fbps_count = g->ops.top.get_max_fbps_count(g); gpu.max_fbps_count = g->ops.top.get_max_fbps_count(g);
gpu.fbp_en_mask = g->ops.gr.get_fbp_en_mask(g); gpu.fbp_en_mask = g->ops.gr.init.get_fbp_en_mask(g);
gpu.max_ltc_per_fbp = g->ops.top.get_max_ltc_per_fbp(g); gpu.max_ltc_per_fbp = g->ops.top.get_max_ltc_per_fbp(g);
gpu.max_lts_per_ltc = g->ops.top.get_max_lts_per_ltc(g); gpu.max_lts_per_ltc = g->ops.top.get_max_lts_per_ltc(g);
gpu.gr_compbit_store_base_hw = g->cbc->compbit_store.base_hw; gpu.gr_compbit_store_base_hw = g->cbc->compbit_store.base_hw;

2
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -426,7 +426,6 @@ static const struct gpu_ops tu104_ops = {
gr_gv11b_update_ctxsw_preemption_mode, gr_gv11b_update_ctxsw_preemption_mode,
.dump_gr_regs = gr_gv11b_dump_gr_status_regs, .dump_gr_regs = gr_gv11b_dump_gr_status_regs,
.update_pc_sampling = gr_gm20b_update_pc_sampling, .update_pc_sampling = gr_gm20b_update_pc_sampling,
.get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
.get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
.init_sm_dsm_reg_info = gr_tu104_init_sm_dsm_reg_info, .init_sm_dsm_reg_info = gr_tu104_init_sm_dsm_reg_info,
.init_cyclestats = gr_gm20b_init_cyclestats, .init_cyclestats = gr_gm20b_init_cyclestats,
@@ -658,6 +657,7 @@ static const struct gpu_ops tu104_ops = {
gv100_gr_hwpm_map_get_active_fbpa_mask, gv100_gr_hwpm_map_get_active_fbpa_mask,
}, },
.init = { .init = {
.get_fbp_en_mask = gm20b_gr_init_get_fbp_en_mask,
.lg_coalesce = gm20b_gr_init_lg_coalesce, .lg_coalesce = gm20b_gr_init_lg_coalesce,
.su_coalesce = gm20b_gr_init_su_coalesce, .su_coalesce = gm20b_gr_init_su_coalesce,
.pes_vsc_stream = gm20b_gr_init_pes_vsc_stream, .pes_vsc_stream = gm20b_gr_init_pes_vsc_stream,