gpu: nvgpu: update common.mc function and docs

- Update documentation for common.mc and gops_mc functions. - Rename test_setup_env and test_free_env to test_mc_setup_env and test_mc_free_env respectively. This will make sure that mc test has independent setup and free functions. - Add doxygen comments for mc.enable and mc.disable. - Modify MC unit test description. Jira NVGPU-6240 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Change-Id: I87291ee5f90b8e3c29c475c00a78c7855de5740e Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457183 (cherry picked from commit c62ff36f87878a8a7513bef06e111117d96c61c8) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480602 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2025-12-25 11:04:51 +03:00 · 2020-12-10 13:09:28 -08:00
parent d1e836f059
commit 26fc64fb0b
6 changed files with 111 additions and 93 deletions
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -1226,7 +1226,6 @@ static const struct gops_mc gv11b_ops_mc = {
 #endif
 	.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
 	.is_stall_and_eng_intr_pending = gv11b_mc_is_stall_and_eng_intr_pending,
-
 #ifdef CONFIG_NVGPU_LS_PMU
 	.is_enabled = gm20b_mc_is_enabled,
 #endif
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -61,31 +61,25 @@ struct gops_mc {
 	 *
 	 * Steps:
 	 * - Read the register mc_boot_0_r().
-	 * - If value is not #U32_MAX
-	 *   - Set in \a arch, the value obtained by mc_boot_0_architecture_v()
-	 *     of the read value shifting left by #NVGPU_GPU_ARCHITECTURE_SHIFT.
-	 *   - Set in \a impl, the value obtained by
-	 *     mc_boot_0_implementation_v() of the read value.
-	 *   - Set in \a rev, value obtained by shifting left
-	 *     mc_boot_0_major_revision_v() of the read value by 4 OR'ing with
-	 *     mc_boot_0_minor_revision_v() of the value.
-	 * - return the value of the register mc_boot_0_r read.
+	 * - Architecture ID is placed in \arch
+	 * - GPU implementation ID is placed in \a impl
+	 * - Chip revision is placed in \a rev
 	 *
-	 * @return value read from mc_boot_0_r().
+	 * @return value of mc_boot_0_r().
 	 */
 	u32 (*get_chip_details)(struct gk20a *g,
 				u32 *arch, u32 *impl, u32 *rev);

 	/**
-	 * @brief Read the the stalling interrupts status register.
+	 * @brief Read the stalling interrupts status register.
 	 *
 	 * @param g [in]	The GPU driver struct.
 	 *
-	 * This function is invoked to get the stalling interrupts reported
+	 * This function is invoked to get stalling interrupts reported
 	 * by the GPU before invoking the ISR.
 	 *
 	 * Steps:
-	 * - Read and return the value of the register
+	 * - Read and return the value of register
 	 *   mc_intr_r(#NVGPU_MC_INTR_STALLING).
 	 *
 	 * @return value read from mc_intr_r(#NVGPU_MC_INTR_STALLING).
@@ -164,8 +158,6 @@ struct gops_mc {
 	 *   handlers.
 	 *   - Invoke g->ops.gr.intr.nonstall_isr if GR interrupt is pending.
 	 *   - Invoke g->ops.ce.isr_nonstall if CE interrupt is pending.
-	 *   These functions return bitmask of operations that are executed on
-	 *   non-stall workqueue.
 	 *
 	 * @return bitmask of operations that are executed on non-stall
 	 * workqueue.
--- a/drivers/gpu/nvgpu/include/nvgpu/mc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/mc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -133,8 +133,8 @@ struct nvgpu_device;
 * @defgroup NVGPU_MC_UNIT_DEFINES
 *
 * Enumeration of all units intended to be used by enabling/disabling HAL
- * that requires unit as parameter. Units are added to the enumeration as
- * needed, so it is not complete.
+ * that requires unit as parameter. Units can be added to the enumeration as
+ * needed.
 */

 /**
@@ -171,12 +171,11 @@ struct nvgpu_device;

 /**
 * @ingroup NVGPU_MC_INTR_TYPE_DEFINES
- */
-/**
 * Index for accessing registers corresponding to stalling interrupts.
 */
 #define NVGPU_MC_INTR_STALLING		0U
 /**
+ * @ingroup NVGPU_MC_INTR_TYPE_DEFINES
 * Index for accessing registers corresponding to non-stalling
 * interrupts.
 */
@@ -195,26 +194,53 @@ struct nvgpu_device;

 /**
 * @ingroup NVGPU_MC_INTR_UNIT_DEFINES
+ * MC interrupt for Bus unit.
 */
-/** MC interrupt for Bus unit. */
 #define MC_INTR_UNIT_BUS	0
-/** MC interrupt for PRIV_RING unit. */
+/**
+ * @ingroup NVGPU_MC_INTR_UNIT_DEFINES
+ * MC interrupt for PRIV_RING unit.
+ */
 #define MC_INTR_UNIT_PRIV_RING	1
-/** MC interrupt for FIFO unit. */
+/**
+ * @ingroup NVGPU_MC_INTR_UNIT_DEFINES
+ * MC interrupt for FIFO unit.
+ */
 #define MC_INTR_UNIT_FIFO	2
-/** MC interrupt for LTC unit. */
+/**
+ * @ingroup NVGPU_MC_INTR_UNIT_DEFINES
+ * MC interrupt for LTC unit.
+ */
 #define MC_INTR_UNIT_LTC	3
-/** MC interrupt for HUB unit. */
+/**
+ * @ingroup NVGPU_MC_INTR_UNIT_DEFINES
+ * MC interrupt for HUB unit.
+ */
 #define MC_INTR_UNIT_HUB	4
-/** MC interrupt for GR unit. */
+/**
+ * @ingroup NVGPU_MC_INTR_UNIT_DEFINES
+ * MC interrupt for GR unit.
+ */
 #define MC_INTR_UNIT_GR		5
-/** MC interrupt for PMU unit. */
+/**
+ * @ingroup NVGPU_MC_INTR_UNIT_DEFINES
+ * MC interrupt for PMU unit.
+ */
 #define MC_INTR_UNIT_PMU	6
-/** MC interrupt for CE unit. */
+/**
+ * @ingroup NVGPU_MC_INTR_UNIT_DEFINES
+ * MC interrupt for CE unit.
+ */
 #define MC_INTR_UNIT_CE		7
-/** MC interrupt for NVLINK unit. */
+/**
+ * @ingroup NVGPU_MC_INTR_UNIT_DEFINES
+ * MC interrupt for NVLINK unit.
+ */
 #define MC_INTR_UNIT_NVLINK	8
-/** MC interrupt for FBPA unit. */
+/**
+ * @ingroup NVGPU_MC_INTR_UNIT_DEFINES
+ * MC interrupt for FBPA unit.
+ */
 #define MC_INTR_UNIT_FBPA	9

 /**
@@ -240,14 +266,14 @@ struct nvgpu_device;
 * interrupt handling of the units/engines.
 */
 struct nvgpu_mc {
-	/** Lock to access the MC interrupt registers */
+	/** Lock to access the MC interrupt registers. */
 	struct nvgpu_spinlock intr_lock;

-	/** Lock to access the mc_enable_r */
+	/** Lock to access the MC unit registers. */
 	struct nvgpu_spinlock enable_lock;

 	/**
-	 * Bitmask of the stalling/non-stalling interrupts enabled.
+	 * Bitmask of the stalling/non-stalling enabled interrupts.
 	 * This is used to enable/disable the interrupts at runtime.
 	 * intr_mask_restore[2] & intr_mask_restore[3] are applicable
 	 * when GSP exists.
@@ -255,31 +281,32 @@ struct nvgpu_mc {
 	u32 intr_mask_restore[4];

 	/**
-	 * Below are the counters & condition varibles needed to keep track of
-	 * the deferred interrupts.
-	 */
-
-	/**
+	 * One of the condition variables needed to keep track of deferred
+	 * interrupts.
 	 * The condition variable that is signalled upon handling of the
-	 * stalling interrupt. It is wait upon by the function
-	 * #nvgpu_wait_for_deferred_interrupts.
+	 * stalling interrupt. Function #nvgpu_wait_for_deferred_interrupts
+	 * waits on this condition variable.
 	 */
 	struct nvgpu_cond sw_irq_stall_last_handled_cond;

 	/**
+	 * One of the counters needed to keep track of deferred interrupts.
 	 * Stalling interrupt status counter - Set to 1 on entering stalling
 	 * interrupt handler and reset to 0 on exit.
 	 */
 	nvgpu_atomic_t sw_irq_stall_pending;

 	/**
+	 * One of the condition variables needed to keep track of deferred
+	 * interrupts.
 	 * The condition variable that is signalled upon handling of the
-	 * non-stalling interrupt. It is wait upon by the function
-	 * #nvgpu_wait_for_deferred_interrupts.
+	 * non-stalling interrupt. Function #nvgpu_wait_for_deferred_interrupts
+	 * waits on this condition variable.
 	 */
 	struct nvgpu_cond sw_irq_nonstall_last_handled_cond;

 	/**
+	 * One of the counters needed to keep track of deferred interrupts.
 	 * Non-stalling interrupt status counter - Set to 1 on entering
 	 * non-stalling interrupt handler and reset to 0 on exit.
 	 */
@@ -299,8 +326,8 @@ struct nvgpu_mc {
 * @param g [in]	The GPU driver struct.
 *
 * While freeing the channel or entering SW quiesce state, nvgpu driver needs
- * to waits until all interrupt handlers that have been scheduled to run have
- * completed as those could access channel after freeing.
+ * to wait until all scheduled interrupt handlers have completed. This is
+ * because the interrupt handlers could access data structures after freeing.
 * Steps:
 * - Get the stalling and non-stalling interrupts atomic count.
 * - Wait on the condition variable #sw_irq_stall_last_handled_cond until
@@ -339,8 +366,8 @@ void nvgpu_mc_intr_enable(struct gk20a *g);
 #endif

 /**
- * @brief Enable the stalling interrupts for GPU unit at the master
- *        level.
+ * @brief Enable/Disable the stalling interrupts for given GPU unit at the
+ *        master level.
 *
 * @param g [in]	The GPU driver struct.
 * @param unit [in]	Value designating the GPU HW unit/engine
@@ -360,8 +387,8 @@ void nvgpu_mc_intr_enable(struct gk20a *g);
 *			  - #MC_INTR_ENABLE
 *			  - #MC_INTR_DISABLE
 *
- * This function is invoked during individual unit's init before
- * enabling that unit's interrupts.
+ * During a unit's init routine, this function is invoked to enable the
+ * unit's stall interrupts.
 *
 * Steps:
 * - Acquire the spinlock g->mc.intr_lock.
@@ -381,8 +408,8 @@ void nvgpu_mc_intr_enable(struct gk20a *g);
 void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);

 /**
- * @brief Enable the non-stalling interrupts for GPU unit at the master
- *        level.
+ * @brief Enable/Disable the non-stalling interrupts for given GPU unit at the
+ *        master level.
 *
 * @param g [in]	The GPU driver struct.
 * @param unit [in]	Value designating the GPU HW unit/engine
@@ -402,8 +429,8 @@ void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
 *			  - #MC_INTR_ENABLE
 *			  - #MC_INTR_DISABLE
 *
- * This function is invoked during individual unit's init before
- * enabling that unit's interrupts.
+ * During a unit's init routine, this function is invoked to enable the
+ * unit's nostall interrupts.
 *
 * Steps:
 * - Acquire the spinlock g->mc.intr_lock.
@@ -448,8 +475,8 @@ void nvgpu_mc_intr_stall_pause(struct gk20a *g);
 *
 * Steps:
 * - Acquire the spinlock g->mc.intr_lock.
- * - Enable the stalling interrupts as configured during #intr_stall_unit_config
- *   Write #intr_mask_restore[#NVGPU_MC_INTR_STALLING] to the stalling
+ * - Enable stalling interrupts as configured during #intr_stall_unit_config
+ * - Write #intr_mask_restore[#NVGPU_MC_INTR_STALLING] to the stalling
 *   interrupts enable set register (mc_intr_en_set_r(#NVGPU_MC_INTR_STALLING)).
 * - Release the spinlock g->mc.intr_lock.
 */
@@ -481,9 +508,9 @@ void nvgpu_mc_intr_nonstall_pause(struct gk20a *g);
 *
 * Steps:
 * - Acquire the spinlock g->mc.intr_lock.
- * - Enable the stalling interrupts as configured during
+ * - Enable non-stalling interrupts as configured during
 *   #intr_nonstall_unit_config.
- *   Write #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING]
+ * - Write #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING]
 *   to the non-stalling interrupts enable set register
 *   (mc_intr_en_set_r(#NVGPU_MC_INTR_NONSTALLING)).
 * - Release the spinlock g->mc.intr_lock.
--- a/userspace/required_tests.ini
+++ b/userspace/required_tests.ini
@@ -322,14 +322,14 @@ test_writel_check.writel_check=0

 [mc]
 test_enable_disable_reset.enable_disable_reset=0
-test_free_env.mc_free_env=0
 test_intr_stall.intr_stall=0
 test_is_intr1_pending.is_intr1_pending=0
 test_is_stall_and_eng_intr_pending.intr_is_stall_and_eng_intr_pending=2
 test_isr_nonstall.isr_nonstall=2
 test_isr_stall.isr_stall=2
+test_mc_free_env.mc_free_env=0
+test_mc_setup_env.mc_setup_env=0
 test_pause_resume_mask.pause_resume_mask=0
-test_setup_env.mc_setup_env=0
 test_unit_config.unit_config=2
 test_wait_for_deferred_interrupts.wait_for_deferred_interrupts=0

--- a/userspace/units/mc/nvgpu-mc.c
+++ b/userspace/units/mc/nvgpu-mc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -197,7 +197,7 @@ static void mock_priv_ring_isr(struct gk20a *g)
 	u.priv_ring_isr = true;
 }

-int test_setup_env(struct unit_module *m,
+int test_mc_setup_env(struct unit_module *m,
 			  struct gk20a *g, void *args)
 {
 	/* Create mc register space */
@@ -254,7 +254,7 @@ int test_setup_env(struct unit_module *m,
 	return UNIT_SUCCESS;
 }

-int test_free_env(struct unit_module *m, struct gk20a *g, void *args)
+int test_mc_free_env(struct unit_module *m, struct gk20a *g, void *args)
 {
 	/* Free mc register space */
 	nvgpu_posix_io_delete_reg_space(g, MC_ADDR_SPACE_START);
@@ -683,7 +683,7 @@ int test_wait_for_deferred_interrupts(struct unit_module *m, struct gk20a *g,
 }

 struct unit_module_test mc_tests[] = {
-	UNIT_TEST(mc_setup_env,			test_setup_env,				NULL, 0),
+	UNIT_TEST(mc_setup_env,			test_mc_setup_env,			NULL, 0),
 	UNIT_TEST(unit_config,			test_unit_config,			NULL, 2),
 	UNIT_TEST(pause_resume_mask,		test_pause_resume_mask,			NULL, 0),
 	UNIT_TEST(intr_stall,			test_intr_stall,			NULL, 0),
@@ -694,7 +694,7 @@ struct unit_module_test mc_tests[] = {
 	UNIT_TEST(is_intr1_pending,		test_is_intr1_pending,			NULL, 0),
 	UNIT_TEST(enable_disable_reset,		test_enable_disable_reset,		NULL, 0),
 	UNIT_TEST(wait_for_deferred_interrupts,	test_wait_for_deferred_interrupts,	NULL, 0),
-	UNIT_TEST(mc_free_env,			test_free_env,				NULL, 0),
+	UNIT_TEST(mc_free_env,			test_mc_free_env,			NULL, 0),
 };

 UNIT_MODULE(mc, mc_tests, UNIT_PRIO_NVGPU_TEST);
--- a/userspace/units/mc/nvgpu-mc.h
+++ b/userspace/units/mc/nvgpu-mc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -33,7 +33,7 @@ struct unit_module;
 */

 /**
- * Test specification for: test_setup_env
+ * Test specification for: test_mc_setup_env
 *
 * Description: Do basic setup before starting other tests.
 *
@@ -50,17 +50,17 @@ struct unit_module;
 * - UNIT_FAIL if encounters an error creating reg space
 * - UNIT_SUCCESS otherwise
 */
-int test_setup_env(struct unit_module *m,
+int test_mc_setup_env(struct unit_module *m,
 			  struct gk20a *g, void *args);

 /**
- * Test specification for: test_free_env
+ * Test specification for: test_mc_free_env
 *
 * Description: Do basic setup before starting other tests.
 *
 * Test Type: Other (setup)
 *
- * Input: test_setup_env has run.
+ * Input: test_mc_setup_env has run.
 *
 * Steps:
 * - Free reg spaces.
@@ -69,7 +69,7 @@ int test_setup_env(struct unit_module *m,
 *
 * Output: UNIT_SUCCESS always.
 */
-int test_free_env(struct unit_module *m, struct gk20a *g, void *args);
+int test_mc_free_env(struct unit_module *m, struct gk20a *g, void *args);

 /**
 * Test specification for: test_unit_config
@@ -82,7 +82,7 @@ int test_free_env(struct unit_module *m, struct gk20a *g, void *args);
 * Targets: nvgpu_mc_intr_stall_unit_config, nvgpu_mc_intr_nonstall_unit_config,
 *          mc_gp10b_intr_stall_unit_config, mc_gp10b_intr_nonstall_unit_config
 *
- * Input: test_setup_env must have been run.
+ * Input: test_mc_setup_env must have been run.
 *
 * Steps:
 * - Set each of the mock registers for enabling & disabling the stall &
@@ -114,7 +114,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args);
 /**
 * Test specification for: test_pause_resume_mask
 *
- * Description: Validate function for pausing, resuming, and masking interrupts.
+ * Description: Validate pausing, resuming and masking interrupts functionality.
 *
 * Test Type: Feature
 *
@@ -124,7 +124,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args);
 *          mc_gp10b_intr_stall_resume, mc_gp10b_intr_nonstall_pause,
 *          mc_gp10b_intr_nonstall_resume, mc_gp10b_intr_mask
 *
- * Input: test_setup_env must have been run.
+ * Input: test_mc_setup_env must have been run.
 *
 * Steps:
 * - Clear each of the mock registers for enabling & disabling the stall &
@@ -151,19 +151,18 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args);
 /**
 * Test specification for: test_intr_stall
 *
- * Description: Validate function mc_gp10b_intr_stall which returns the pending
- *              interrupts.
+ * Description: Validate stalling interrupt pending status check.
 *
 * Test Type: Feature
 *
 * Targets: gops_mc.intr_stall, mc_gp10b_intr_stall
 *
- * Input: test_setup_env must have been run.
+ * Input: test_mc_setup_env must have been run.
 *
 * Steps:
 * - Loop through setting each bit individually in the stall interrupt pending
 *   register:
- *   - For iteration, call the HAL and verify the correct value is returned.
+ *   - For each iteration, call HAL and verify that correct value is returned.
 *
 * Output: Returns PASS if expected result is met, FAIL otherwise.
 */
@@ -172,20 +171,22 @@ int test_intr_stall(struct unit_module *m, struct gk20a *g, void *args);
 /**
 * Test specification for: test_is_stall_and_eng_intr_pending
 *
- * Description: Validate function of HAL gv11b_mc_is_stall_and_eng_intr_pending.
+ * Description: Validate stalling or engine interrupt pending functionality.
 *
 * Test Type: Feature
 *
 * Targets: gops_mc.is_stall_and_eng_intr_pending,
 *          gv11b_mc_is_stall_and_eng_intr_pending
 *
- * Input: test_setup_env must have been run.
+ * Input: test_mc_setup_env must have been run.
 *
 * Steps:
 * - Clear the stall interrupt pending register.
- * - Call the HAL API and verify it returns false since nothing is pending.
+ * - Call gops_mc.is_stall_and_eng_intr_pending and verify that return value is
+ *   false since nothing is pending.
 * - Set all interrupts pending in the stall interrupt pending register.
- * - Call the HAL API and verify it returns true and the correct pending mask.
+ * - Verify gops_mc.is_stall_and_eng_intr_pending returns true with correct
+ *   pending mask.
 *
 * Output: Returns PASS if expected result is met, FAIL otherwise.
 */
@@ -195,14 +196,14 @@ int test_is_stall_and_eng_intr_pending(struct unit_module *m, struct gk20a *g,
 /**
 * Test specification for: test_isr_stall
 *
- * Description: Validate handling of the stall interrupts by the stall interrupt
+ * Description: Validate handling of stall interrupts by the stall interrupt
 *              service routine.
 *
 * Test Type: Feature
 *
 * Targets: gops_mc.isr_stall, mc_gp10b_isr_stall
 *
- * Input: test_setup_env must have been run.
+ * Input: test_mc_setup_env must have been run.
 *
 * Steps:
 * - Clear the stall interrupt pending register.
@@ -233,15 +234,15 @@ int test_isr_stall(struct unit_module *m, struct gk20a *g, void *args);
 /**
 * Test specification for: test_isr_nonstall
 *
- * Description: Validate handling of the stall interrupts by the non-stall
- * 		interrupt service routine.
+ * Description: Validate non-stall interrupt pending status check and their
+ *              handling by the non-stall interrupt service routine.
 *
 * Test Type: Feature
 *
 * Targets: gops_mc.isr_nonstall, gm20b_mc_isr_nonstall, gops_mc.intr_nonstall,
 *          mc_gp10b_intr_nonstall
 *
- * Input: test_setup_env must have been run.
+ * Input: test_mc_setup_env must have been run.
 *
 * Steps:
 * - Clear the non-stall interrupt pending register.
@@ -268,7 +269,7 @@ int test_isr_nonstall(struct unit_module *m, struct gk20a *g, void *args);
 *
 * Targets: gops_mc.is_intr1_pending, mc_gp10b_is_intr1_pending
 *
- * Input: test_setup_env must have been run.
+ * Input: test_mc_setup_env must have been run.
 *
 * Steps:
 * - Call the HAL API, requesting if the FIFO Unit is pending, passing in a
@@ -286,15 +287,14 @@ int test_is_intr1_pending(struct unit_module *m, struct gk20a *g, void *args);
 /**
 * Test specification for: test_enable_disable_reset
 *
- * Description: Validate functionality of functions for enabling, disabling,
- *              and reseting units.
+ * Description: Validate enabling, disabling and resetting units functionality.
 *
 * Test Type: Feature
 *
 * Targets: gops_mc.enable, gops_mc.disable, gops_mc.reset, gm20b_mc_enable,
 *           gm20b_mc_disable, gm20b_mc_reset
 *
- * Input: test_setup_env must have been run.
+ * Input: test_mc_setup_env must have been run.
 *
 * Steps:
 * - Call the enable HAL API to enable units.
@@ -317,7 +317,7 @@ int test_enable_disable_reset(struct unit_module *m, struct gk20a *g, void *args
 *
 * Targets: gops_mc.reset_mask, gm20b_mc_reset_mask
 *
- * Input: test_setup_env must have been run.
+ * Input: test_mc_setup_env must have been run.
 *
 * Steps:
 * - Call the enable HAL API for a number of units and verify the correct
@@ -338,7 +338,7 @@ int test_reset_mask(struct unit_module *m, struct gk20a *g, void *args);
 *
 * Targets: nvgpu_wait_for_deferred_interrupts
 *
- * Input: test_setup_env must have been run.
+ * Input: test_mc_setup_env must have been run.
 *
 * Steps:
 * - Initialize cond structures required by the API.