nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-25 02:52:51 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: update common.mc function and docs

Browse Source 
- Update documentation for common.mc and gops_mc functions.
- Rename test_setup_env and test_free_env to test_mc_setup_env and
test_mc_free_env respectively. This will make sure that mc test has
independent setup and free functions.
- Add doxygen comments for mc.enable and mc.disable.
- Modify MC unit test description.

Jira NVGPU-6240

Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: I87291ee5f90b8e3c29c475c00a78c7855de5740e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457183
(cherry picked from commit c62ff36f87878a8a7513bef06e111117d96c61c8)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480602
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2020-12-10 13:09:28 -08:00
committed by mobile promotions
parent d1e836f059
commit 26fc64fb0b
6 changed files with 111 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -1226,7 +1226,6 @@ static const struct gops_mc gv11b_ops_mc = {
#endif
.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
.is_stall_and_eng_intr_pending = gv11b_mc_is_stall_and_eng_intr_pending,
#ifdef CONFIG_NVGPU_LS_PMU
.is_enabled = gm20b_mc_is_enabled,
#endif

24
drivers/gpu/nvgpu/include/nvgpu/gops/mc.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -61,31 +61,25 @@ struct gops_mc {
*
* Steps:
* - Read the register mc_boot_0_r().
* - If value is not #U32_MAX
* - Set in \a arch, the value obtained by mc_boot_0_architecture_v()
* of the read value shifting left by #NVGPU_GPU_ARCHITECTURE_SHIFT.
* - Set in \a impl, the value obtained by
* mc_boot_0_implementation_v() of the read value.
* - Set in \a rev, value obtained by shifting left
* mc_boot_0_major_revision_v() of the read value by 4 OR'ing with
* mc_boot_0_minor_revision_v() of the value.
* - return the value of the register mc_boot_0_r read.
* - Architecture ID is placed in \arch
* - GPU implementation ID is placed in \a impl
* - Chip revision is placed in \a rev
*
* @return value read from mc_boot_0_r().
* @return value of mc_boot_0_r().
*/
u32 (*get_chip_details)(struct gk20a *g,
u32 *arch, u32 *impl, u32 *rev);
/**
* @brief Read the the stalling interrupts status register.
* @brief Read the stalling interrupts status register.
*
* @param g [in] The GPU driver struct.
*
* This function is invoked to get the stalling interrupts reported
* This function is invoked to get stalling interrupts reported
* by the GPU before invoking the ISR.
*
* Steps:
* - Read and return the value of the register
* - Read and return the value of register
* mc_intr_r(#NVGPU_MC_INTR_STALLING).
*
* @return value read from mc_intr_r(#NVGPU_MC_INTR_STALLING).
@@ -164,8 +158,6 @@ struct gops_mc {
* handlers.
* - Invoke g->ops.gr.intr.nonstall_isr if GR interrupt is pending.
* - Invoke g->ops.ce.isr_nonstall if CE interrupt is pending.
* These functions return bitmask of operations that are executed on
* non-stall workqueue.
*
* @return bitmask of operations that are executed on non-stall
* workqueue.

109
drivers/gpu/nvgpu/include/nvgpu/mc.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -133,8 +133,8 @@ struct nvgpu_device;
* @defgroup NVGPU_MC_UNIT_DEFINES
*
* Enumeration of all units intended to be used by enabling/disabling HAL
* that requires unit as parameter. Units are added to the enumeration as
* needed, so it is not complete.
* that requires unit as parameter. Units can be added to the enumeration as
* needed.
*/
/**
@@ -171,12 +171,11 @@ struct nvgpu_device;
/**
* @ingroup NVGPU_MC_INTR_TYPE_DEFINES
*/
/**
* Index for accessing registers corresponding to stalling interrupts.
*/
#define NVGPU_MC_INTR_STALLING 0U
/**
* @ingroup NVGPU_MC_INTR_TYPE_DEFINES
* Index for accessing registers corresponding to non-stalling
* interrupts.
*/
@@ -195,26 +194,53 @@ struct nvgpu_device;
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for Bus unit.
*/
/** MC interrupt for Bus unit. */
#define MC_INTR_UNIT_BUS 0
/** MC interrupt for PRIV_RING unit. */
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for PRIV_RING unit.
*/
#define MC_INTR_UNIT_PRIV_RING 1
/** MC interrupt for FIFO unit. */
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for FIFO unit.
*/
#define MC_INTR_UNIT_FIFO 2
/** MC interrupt for LTC unit. */
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for LTC unit.
*/
#define MC_INTR_UNIT_LTC 3
/** MC interrupt for HUB unit. */
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for HUB unit.
*/
#define MC_INTR_UNIT_HUB 4
/** MC interrupt for GR unit. */
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for GR unit.
*/
#define MC_INTR_UNIT_GR 5
/** MC interrupt for PMU unit. */
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for PMU unit.
*/
#define MC_INTR_UNIT_PMU 6
/** MC interrupt for CE unit. */
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for CE unit.
*/
#define MC_INTR_UNIT_CE 7
/** MC interrupt for NVLINK unit. */
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for NVLINK unit.
*/
#define MC_INTR_UNIT_NVLINK 8
/** MC interrupt for FBPA unit. */
/**
* @ingroup NVGPU_MC_INTR_UNIT_DEFINES
* MC interrupt for FBPA unit.
*/
#define MC_INTR_UNIT_FBPA 9
/**
@@ -240,14 +266,14 @@ struct nvgpu_device;
* interrupt handling of the units/engines.
*/
struct nvgpu_mc {
/** Lock to access the MC interrupt registers */
/** Lock to access the MC interrupt registers. */
struct nvgpu_spinlock intr_lock;
/** Lock to access the mc_enable_r */
/** Lock to access the MC unit registers. */
struct nvgpu_spinlock enable_lock;
/**
* Bitmask of the stalling/non-stalling interrupts enabled.
* Bitmask of the stalling/non-stalling enabled interrupts.
* This is used to enable/disable the interrupts at runtime.
* intr_mask_restore[2] & intr_mask_restore[3] are applicable
* when GSP exists.
@@ -255,31 +281,32 @@ struct nvgpu_mc {
u32 intr_mask_restore[4];
/**
* Below are the counters & condition varibles needed to keep track of
* the deferred interrupts.
*/
/**
* One of the condition variables needed to keep track of deferred
* interrupts.
* The condition variable that is signalled upon handling of the
* stalling interrupt. It is wait upon by the function
* #nvgpu_wait_for_deferred_interrupts.
* stalling interrupt. Function #nvgpu_wait_for_deferred_interrupts
* waits on this condition variable.
*/
struct nvgpu_cond sw_irq_stall_last_handled_cond;
/**
* One of the counters needed to keep track of deferred interrupts.
* Stalling interrupt status counter - Set to 1 on entering stalling
* interrupt handler and reset to 0 on exit.
*/
nvgpu_atomic_t sw_irq_stall_pending;
/**
* One of the condition variables needed to keep track of deferred
* interrupts.
* The condition variable that is signalled upon handling of the
* non-stalling interrupt. It is wait upon by the function
* #nvgpu_wait_for_deferred_interrupts.
* non-stalling interrupt. Function #nvgpu_wait_for_deferred_interrupts
* waits on this condition variable.
*/
struct nvgpu_cond sw_irq_nonstall_last_handled_cond;
/**
* One of the counters needed to keep track of deferred interrupts.
* Non-stalling interrupt status counter - Set to 1 on entering
* non-stalling interrupt handler and reset to 0 on exit.
*/
@@ -299,8 +326,8 @@ struct nvgpu_mc {
* @param g [in] The GPU driver struct.
*
* While freeing the channel or entering SW quiesce state, nvgpu driver needs
* to waits until all interrupt handlers that have been scheduled to run have
* completed as those could access channel after freeing.
* to wait until all scheduled interrupt handlers have completed. This is
* because the interrupt handlers could access data structures after freeing.
* Steps:
* - Get the stalling and non-stalling interrupts atomic count.
* - Wait on the condition variable #sw_irq_stall_last_handled_cond until
@@ -339,8 +366,8 @@ void nvgpu_mc_intr_enable(struct gk20a *g);
#endif
/**
* @brief Enable the stalling interrupts for GPU unit at the master
* level.
* @brief Enable/Disable the stalling interrupts for given GPU unit at the
* master level.
*
* @param g [in] The GPU driver struct.
* @param unit [in] Value designating the GPU HW unit/engine
@@ -360,8 +387,8 @@ void nvgpu_mc_intr_enable(struct gk20a *g);
* - #MC_INTR_ENABLE
* - #MC_INTR_DISABLE
*
* This function is invoked during individual unit's init before
* enabling that unit's interrupts.
* During a unit's init routine, this function is invoked to enable the
* unit's stall interrupts.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
@@ -381,8 +408,8 @@ void nvgpu_mc_intr_enable(struct gk20a *g);
void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
/**
* @brief Enable the non-stalling interrupts for GPU unit at the master
* level.
* @brief Enable/Disable the non-stalling interrupts for given GPU unit at the
* master level.
*
* @param g [in] The GPU driver struct.
* @param unit [in] Value designating the GPU HW unit/engine
@@ -402,8 +429,8 @@ void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
* - #MC_INTR_ENABLE
* - #MC_INTR_DISABLE
*
* This function is invoked during individual unit's init before
* enabling that unit's interrupts.
* During a unit's init routine, this function is invoked to enable the
* unit's nostall interrupts.
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
@@ -448,8 +475,8 @@ void nvgpu_mc_intr_stall_pause(struct gk20a *g);
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Enable the stalling interrupts as configured during #intr_stall_unit_config
* Write #intr_mask_restore[#NVGPU_MC_INTR_STALLING] to the stalling
* - Enable stalling interrupts as configured during #intr_stall_unit_config
* - Write #intr_mask_restore[#NVGPU_MC_INTR_STALLING] to the stalling
* interrupts enable set register (mc_intr_en_set_r(#NVGPU_MC_INTR_STALLING)).
* - Release the spinlock g->mc.intr_lock.
*/
@@ -481,9 +508,9 @@ void nvgpu_mc_intr_nonstall_pause(struct gk20a *g);
*
* Steps:
* - Acquire the spinlock g->mc.intr_lock.
* - Enable the stalling interrupts as configured during
* - Enable non-stalling interrupts as configured during
* #intr_nonstall_unit_config.
* Write #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING]
* - Write #intr_mask_restore[#NVGPU_MC_INTR_NONSTALLING]
* to the non-stalling interrupts enable set register
* (mc_intr_en_set_r(#NVGPU_MC_INTR_NONSTALLING)).
* - Release the spinlock g->mc.intr_lock.