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gpu: nvgpu: gv11b: Remove privsecurity from gpu_ops

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Replace privsecurity boolean flag in gpu_ops with entry in
common flag system.

The new common flag is NVGPU_SEC_PRIVSECURITY

Jira NVGPU-74

Change-Id: I4c11e3a89a76abe137cf61b69ad0fbcd665554b7
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1525714
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Sunny He
2017-07-24 12:19:53 -07:00
committed by mobile promotions
parent a5d6970df7
commit 2b98e1308d
5 changed files with 20 additions and 12 deletions
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9
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -25,6 +25,7 @@
#include <nvgpu/dma.h>
#include <nvgpu/log.h>
#include <nvgpu/debug.h>
#include <nvgpu/enabled.h>
#include "gk20a/gk20a.h"
#include "gk20a/gr_gk20a.h"
@@ -3574,7 +3575,7 @@ static void gr_gv11b_init_gpc_mmu(struct gk20a *g)
nvgpu_log_info(g, "initialize gpc mmu");
if (!g->ops.privsecurity) {
if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
/* Bypass MMU check for non-secure boot. For
* secure-boot,this register write has no-effect */
gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff);
@@ -3601,9 +3602,11 @@ static void gr_gv11b_init_gpc_mmu(struct gk20a *g)
gk20a_readl(g, fb_mmu_debug_rd_r()));
}
void gv11b_init_gr(struct gpu_ops *gops)
void gv11b_init_gr(struct gk20a *g)
{
gp10b_init_gr(gops);
struct gpu_ops *gops = &g->ops;
gp10b_init_gr(g);
gops->gr.init_preemption_state = NULL;
gops->gr.init_fs_state = gr_gv11b_init_fs_state;
gops->gr.detect_sm_arch = gr_gv11b_detect_sm_arch;

4
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -29,7 +29,7 @@ struct zbc_s_table {
u32 ref_cnt;
};
struct gpu_ops;
struct gk20a;
enum {
VOLTA_CHANNEL_GPFIFO_A = 0xC36F,
@@ -59,7 +59,7 @@ enum {
#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0
void gv11b_init_gr(struct gpu_ops *ops);
void gv11b_init_gr(struct gk20a *g);
int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size,
struct nvgpu_mem *mem);
/*zcull*/

6
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -358,16 +358,16 @@ int gv11b_init_hal(struct gk20a *g)
gops->get_litter_value = gv11b_ops.get_litter_value;
/* boot in non-secure modes for time beeing */
gops->privsecurity = 0;
__nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
__nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
gv11b_init_gr(gops);
gv11b_init_gr(g);
gv11b_init_fecs_trace_ops(gops);
gv11b_init_fb(gops);
gv11b_init_ce(gops);
gv11b_init_gr_ctx(gops);
gv11b_init_mm(gops);
gv11b_init_pmu_ops(gops);
gv11b_init_pmu_ops(g);
gv11b_init_regops(gops);
gv11b_init_therm_ops(gops);

7
drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
View File

@@ -20,6 +20,7 @@
#include <nvgpu/pmu.h>
#include <nvgpu/falcon.h>
#include <nvgpu/enabled.h>
#include "gk20a/gk20a.h"
@@ -234,9 +235,11 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id)
return 0;
}
void gv11b_init_pmu_ops(struct gpu_ops *gops)
void gv11b_init_pmu_ops(struct gk20a *g)
{
gp10b_init_pmu_ops(gops);
struct gpu_ops *gops = &g->ops;
gp10b_init_pmu_ops(g);
gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap;
gops->pmu.is_pmu_supported = gv11b_is_pmu_supported;
gops->pmu.reset_engine = gp106_pmu_engine_reset;

6
drivers/gpu/nvgpu/gv11b/pmu_gv11b.h
View File

@@ -1,7 +1,7 @@
/*
* GV11B PMU
*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -16,6 +16,8 @@
#ifndef __PMU_GV11B_H_
#define __PMU_GV11B_H_
void gv11b_init_pmu_ops(struct gpu_ops *gops);
struct gk20a;
void gv11b_init_pmu_ops(struct gk20a *g);
#endif /*__PMU_GV11B_H_*/