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gpu: nvgpu: gp10b: Disable RE suppression

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Bug 1642669

Change-Id: I683338256b7f2a165a7933aa59de510eb109ea6f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/755150
Reviewed-by: Automatic_Commit_Validation_User
This commit is contained in:
Terje Bergstrom
2015-06-03 15:53:12 -07:00
committed by Deepak Nibade
parent 910bb6ad0d
commit 3b5a1295fa
2 changed files with 21 additions and 0 deletions
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5
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -916,6 +916,11 @@ static int gr_gp10b_init_fs_state(struct gk20a *g)
gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f());
gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data);
data = gk20a_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r());
data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(),
gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f());
gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data);
return gr_gm20b_ctx_state_floorsweep(g);
}

16
drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
View File

@@ -3766,8 +3766,24 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
{
return (v & 0x7) << 8;
}
static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
{
return 0x7 << 8;
}
static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
{
return 0x100;
}
static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
{
return 0x00419f78;
}
static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
{
return 0x3 << 11;
}
static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
{
return 0x1000;
}
#endif