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gpu: nvgpu: regops: fix MISRA 10.3 violations

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MISRA Rule 10.3 prohibits assignment of objects of different essential
or narrower type. This fixes a number of MISRA 10.3 violations in
the common/regops unit.

JIRA: NVGPU-3023

Change-Id: Iee51780f8a570de79ae7a5e23517a48b2da51fef
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084206
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-03-28 16:23:24 -04:00
committed by mobile promotions
parent a762c87c17
commit 3c83b44544
1 changed files with 5 additions and 9 deletions
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14
drivers/gpu/nvgpu/common/regops/regops.c
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@@ -45,9 +45,9 @@ static int regop_bsearch_range_cmp(const void *pkey, const void *pelem)
return 1;
}
static inline bool linear_search(u32 offset, const u32 *list, int size)
static inline bool linear_search(u32 offset, const u32 *list, u64 size)
{
int i;
u64 i;
for (i = 0; i < size; i++) {
if (list[i] == offset) {
return true;
@@ -68,17 +68,13 @@ static inline bool linear_search(u32 offset, const u32 *list, int size)
*/
static bool gr_context_info_available(struct gr_gk20a *gr)
{
int err;
bool initialized;
nvgpu_mutex_acquire(&gr->ctx_mutex);
err = !gr->ctx_vars.golden_image_initialized;
initialized = gr->ctx_vars.golden_image_initialized;
nvgpu_mutex_release(&gr->ctx_mutex);
if (err != 0) {
return false;
}
return true;
return initialized;
}
static bool validate_reg_ops(struct gk20a *g,